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AMDK11
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AMDK11
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
Does it hinder HPC from achieving higher scalability with SMT?
Yesterday at 11:02 AM
A
AMDK11
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
Or cluster decoding is not the best solution for a single thread. However, this is the best solution for hyper-threading (SMT), similar...
Sunday at 6:45 AM
A
AMDK11
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
What the hell. Zen5 has a 2x 4-way decoder (a solution similar to Intel's Tremont-Gracemont), a drop in UOP cache from 6000 (Zen4) to...
Saturday at 3:28 PM
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
I deliberately used simplification. I just wanted to emphasize that the profits often do not even reach 50% of the amount of resources...
Saturday at 9:32 AM
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
On average +14% IPC is without AVX512 and HT. The IPC curve of Zen 4 and Zen 5 includes AVX512 and probably SMT. Going from ALU 5 to 6...
Saturday at 8:14 AM
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
Regarding Lion Cove, Intel, emphasizing the division of the schedule into separate for ALU and separate for FPU, shows P-Core graphics...
Friday at 7:44 PM
A
AMDK11
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
"deeper window size across design for more parallelism"
Friday at 1:20 PM
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
I don't deny that you may be right.
Thursday at 3:02 PM
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
They could remove the HT logic from the core, so they could also remove the ADD, FMA, ROB, etc. transistors specifically for LunarLake...
Thursday at 3:00 PM
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
Moreover, the IPC curve of SunnyCove, GoldenCove, Zen4 and Zen5 most likely also includes SMT/HT, which also affects the average IPC...
Jun 19, 2024
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
Take into account that the Zen5 IPC curve includes AVX512 while the LionCove IPC curve does not. IPC curve (average +19%) GoldenCove...
Jun 19, 2024
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
Here's why. Until now, all processors, whether mobile, Core or Xeon, used exactly the same P-Core. Intel itself, together with LionCove...
Jun 19, 2024
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
LionCove has not said its last word yet. We will see how dividing schedules into separate ones for ALU and separate ones for FPU will...
Jun 19, 2024
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
LionCove at ArrowLake will be different. Intel itself admitted that logic was removed from the LunarLake variant to save space and power...
Jun 19, 2024
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
In my humble opinion, LionCove is a new approach to core design and construction methodology. Since the beginning, Intel has used a...
Jun 19, 2024
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