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A
AMDK11
replied to the thread
Discussion
Intel current and future Lakes & Rapids thread
.
I know that. It seems strange that there would be two different architectures between GoldenCove and LionCove? I know these are...
May 23, 2024
A
AMDK11
replied to the thread
Discussion
Intel current and future Lakes & Rapids thread
.
RedwoodCove in Xeon looks exactly the same as in MeteorLake. Intel just isn't bragging about the IPC improvements in Meteorlake because...
May 23, 2024
A
AMDK11
replied to the thread
Discussion
Intel current and future Lakes & Rapids thread
.
It all depends on how much of an IPC increase LionCove achieves and how it compares to Zen 5. LionCove is supposed to be enough for 2...
May 21, 2024
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
I understand what you are saying that going from 3x FP-ALU and 2x ALU to 4x FPU and 6x ALU, i.e. + 2x more, is misleading. I am aware of...
May 20, 2024
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
A slightly better, clearer diagram of the LionCove core:
May 20, 2024
A
AMDK11
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
Here you go. I know I'm repeating myself, but the only sticking point when it comes to LionCove is this unlabeled graphic diagram from...
May 19, 2024
A
AMDK11
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
I think that the topic of the impact of cache and delays on IPC has been developed so much that it is obvious. Let's go ahead and...
May 10, 2024
A
AMDK11
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
A processor with a 0.2 ms latch can process more instructions per cycle than a processor with a 0.3 ms latch. Less downtime means the...
May 10, 2024
A
AMDK11
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
Core architecture changes + unified L3 cache as a whole architecture. I don't know how you can still think that L3 was completely...
May 10, 2024
A
AMDK11
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
RaptorLake has no inter-chiplet latency problem and the RAM controller is on the same chip. Thanks to 2MB L2 instead of 1.25MB...
May 10, 2024
A
AMDK11
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
V Cache is a lot of additional billions of transistors to obtain additional IPC layers from the cores. VCache only allows you to get...
May 10, 2024
A
AMDK11
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
Everything matters. Games benefit mainly from this. Just a moment ago you said that you don't see the difference, that each core has...
May 10, 2024
A
AMDK11
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
And did I write somewhere that there are no other improvements apart from the cache? VCache clearly shows that reducing latency in...
May 10, 2024
A
AMDK11
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
I see this is still a problem. CCD Zen 2 has 2x CCX(4 cores and 16MB) (2x 16 MB (total 32 MB)). The problem is that each Zen2 core...
May 9, 2024
A
AMDK11
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
At what point am I wrong? Enlighten me. Sorry. My fault. I took this post in the wrong context. The topic is mainly addressed to the...
May 9, 2024
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