Recent content by AMDK11

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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

The LionCove core itself is a reset if we are to strictly adhere to Intel's tradition in this matter. It is a bit strange that the C&C analyses show that the predictor is also lame in some respects compared to RaptorCove, even though Intel claims that this part is 8x larger in some respects...
- AMDK11
- Post #19,133
- Mar 23, 2025
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Chips and Cheese:
- AMDK11
- Post #15,621
- Oct 25, 2024
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

In the case of Skymont, it is more difficult for me to recognize the structures. I found the description, but it looks like someone confused Front-end with Back-end (I think). In ArrowLake's LionCove variant, there is a larger space between the lower half of L2 and the upper half of L2, so...
- AMDK11
- Post #15,057
- Oct 22, 2024
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Delete
- AMDK11
- Post #15,055
- Oct 22, 2024
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

I didn't forget. L2 3MB is the lion's share of LionCove core. You can clearly see that in ArrowLake it is 512KB(0.5MB) bigger than the variant in LunarLake(L2 2.5MB).
- AMDK11
- Post #15,053
- Oct 22, 2024
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Including larger Front-End, 8x wider predictor, 8-Wide decode, L1-I 64KB, UOP Cache(L0) 5250, Queue 192, ROB 576, Branch Order Buffer 180, Scheduler FP 114 and PRF ~400, Scheduler INT 97 and PRF 290, Execution units on 10 (4x FP + 6x ALU) ports instead of 5 (3x FP/ALU + 2x ALU)...
- AMDK11
- Post #15,050
- Oct 22, 2024
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Lower clock speeds, densely packed Skymont core logic, smaller structures including buffers. There is no great philosophy here. See on Zen4c compared to Zen4 while maintaining the same IPC, the surface area of Zen4c is much smaller(-34%). The same was done with Skymont, plus less extensive core...
- AMDK11
- Post #14,827
- Oct 18, 2024
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Apple in Mx and ARM adds a total of 8 ALUs, gaining a significant IPC increase for INT, but in your opinion Skymont adds 2x more for no reason? This has absolutely no impact on the IPC increase for Integer (sarcasm) :D Core: Crestmont Skymont Integer...
- AMDK11
- Post #14,825
- Oct 18, 2024
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

LionCove has ALU with more MUL, SHIFT and Branch. There are more of these units in ALU LionCove. The fact is that Skymont with 8xALU reaches the IPC level of RaptorCove with 5xALU, and LionCove has 6xALU. Gracemont also doesn't have the more complicated ALUs and in that respect Skymont adds...
- AMDK11
- Post #14,817
- Oct 18, 2024
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Look at it from a different perspective. Skymont gains this IPC increase for Integer at 8x ALU compared to 6x ALU in LionCove and 4x ALU in Gracemont, for FP 4x 128bit compared to LionCove 2x 256/128bit and Gracemont 2x FP 128bit. Skymont achieves this IPC with a 3x3-wide (total 9-wide)...
- AMDK11
- Post #14,815
- Oct 18, 2024
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

This is just a hypothesis, as Netbrust has never had a larger number of execution units or a wider decoder in any generation. How Netbrust would behave if the next generation had a decoder width of 2 instead of 1 is pure hypothesis. Netbrust has never fought for a higher IPC. Netbrust is a...
- AMDK11
- Post #14,813
- Oct 18, 2024
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

The fact that Gracemont (2021) achieved IPC Skylake (2015) and Skymont (2024) achieved IPC GoldenCove/RaptorCove (2021-2022) is not indicative of the size of the Skymont team. If you have time and many years to build a core from an IPC from several years ago, with different solutions and...
- AMDK11
- Post #14,811
- Oct 18, 2024
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Pentium 4 never had more than a 1-Way decoder and even in its last incarnation it was not intended to have a higher IPC but to achieve even higher clock speeds. Compared to GoldenCove, LionCove, despite dividing the execution engine into a separate one for FP and a separate one for ALU and...
- AMDK11
- Post #14,676
- Oct 16, 2024
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

What changes took place inside Intel and the merger of the P and E teams is one thing, but interpreting it without knowing the details is just hypotheses and theories. My hypothesis is that the P and e cores are supposed to be more aligned for ISA. The fact that the ideas of some can migrate to...
- AMDK11
- Post #14,521
- Oct 13, 2024
- Forum: CPUs and Overclocking
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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

No, LionCove is the first Intel core since 1995 to introduce separate schedulers and pipelines for FP and separate ones for ALU. The tiles add to this a delay compared to RaptorCove.
- AMDK11
- Post #14,518
- Oct 13, 2024
- Forum: CPUs and Overclocking

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