I'm saying the Zen 5C variant also exhibits that same trait. Each CPU is supposed to do 1510 while two CPUs manage to miraculously do 1550 per CPU.
It doesn't seem to be a typo, but due to the litany of potential reasons the other people have posted in this thread.
Pretty sure Zen 5 is ahead...
And yet GNR is within striking range of Turin classic.
Diamond Rapids should have P-cores with similar IPC vs Venice too, something which GNR did not enjoy.
You are seeing ghosts dude. Not a single person here is saying GNR is better than Turin lol.
Wdym
Igh dude lol.
The term BOM was never once mentioned in that comment, because no one was talking about it up till now lol.
Who ever said GNR was the better product?
Why do you think that would happen?
This prob will end up being true. We will see though.
You aren't him, bro.
Could be, honestly, idk, but...
Which picture do you think is more accurate? The one posted by AMD themselves at an actual tech conference, or Phoronix?
EMR ended up looking so much closer to AMD than it should have been due to this
True
Look at who you are quoting lol
lol
The CPU in question is Turin, and the data is...
I mean GNR is already competitive with Turin standard iso power, according to AMD. Turin Dense has like a 25% lead.
I fully expect Intel's server position relative to AMD to only get better from here, since they are releasing more competitive products compared to EMR vs Genoa, and GNR ramps.
Area
Two measurements I think are the most important: CCX and Core only (not including core private L2/L1.5)
CCX encapsulates the entire CPU area of the SOC
Core only area to evaluate specifically the core IP itself.
The reason I did not include the L2 (despite it being core private) is that...
Ways of measuring Area- including L2, SLC?
Ways of measuring Power- what sort of workloads for evaluating CPU and "CCX" power?
Ways of measuring Performance- what sort of performance and at what tiers of power should performance be evaluated?
AMD engineers claimed they under-achieved their Zen 4 Fmax goals. I don't think, unless AMD increased nT power draw for Zen 5 while keeping the all core boost of Zen 4 arbitrarily low, Zen 5 was going to be a large upgrade in traditional nT perf.
I don't think Zen 5 is a bad uplift totally...
Some interesting stuff IMO:
AMD confirms Zen 5 power cross over point with Zen 4, once again I should mention this was not mentioned for the Zen 3 to Zen 2 jump. I really do believe whatever magic sauce AMD had with the Zen 3 jump was not present with the Zen 5 jump.
Majority of 8T SRAM is now...
GNR appears to have a pretty slow ramp/volume issues.
Not only is it rumors, I think Gelsinger even confirmed it in an earnings call or some tech conference (some off hand remark about DMR using a new platform) a while back. I couldn't dig it up from a short search so I may be misremembering...
@SiliconFly What you are doing on twitter man is pathetic dude. But I also shouldn't have fallen for the obvious rage bait, that's on me.
Also, I love silicon? Really? Should be I love INTEL silicon.
I think even if they increase core area a decent bit, the fact that so much of the total chiplet is still SRAM means that looking at the total CCD area %, it wouldn't be that bad for margins.
Plus, apparently NVL's P cores cut down the L2 cache capacity a bit since they are doing the shared...
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