Recent content by Gnyueh

Question AMD Rembrandt/Zen 3+ APU Speculation and Discussion

The mess for oem's could be far more than just socket.
- Gnyueh
- Post #768
- Dec 6, 2021
- Forum: CPUs and Overclocking
Question AMD Rembrandt/Zen 3+ APU Speculation and Discussion

OEMs are always relunctant to make laptops based on such platform that is originally designed for desktop.
- Gnyueh
- Post #761
- Dec 5, 2021
- Forum: CPUs and Overclocking
Question The IF interconnect topology inside sIOD of ROME?

NPS4 will be better for ROME because interleave the 8 ch mem will make the cross-die XGMI a bottle-neck which works@memclk/2 2ch mem bw?
- Gnyueh
- Post #12
- Feb 5, 2020
- Forum: CPUs and Overclocking
Question The IF interconnect topology inside sIOD of ROME?

unidirectional means one-direction? Sorry for that confusion. The author's reply: unidirectional ring is my previous conjecture. Now after several people have tested it for several nights, it can be determined that it is linear. For a linear topology, the nodes in the middle will have...
- Gnyueh
- Post #9
- Feb 4, 2020
- Forum: CPUs and Overclocking
Question The IF interconnect topology inside sIOD of ROME?

I closed ring will be a 4 step ladder inside CCX -> inside IOD slice -> closest slice -> diagonal slice
- Gnyueh
- Post #7
- Feb 4, 2020
- Forum: CPUs and Overclocking
Question The IF interconnect topology inside sIOD of ROME?

This topolgy is still more a hypothesis than a confirmed conclusion, and the debate is heated up at CHH. For now the conclusion seems correct ( 5-step ladder is confirmed by cross-core data coherency ping-pong tool (cache irrelavent) by LambdaDelta...
- Gnyueh
- Post #5
- Feb 3, 2020
- Forum: CPUs and Overclocking
Question The IF interconnect topology inside sIOD of ROME?

Some interestiing experiment to scope into sIOD's interconnect by test core to core ping at Chiphell https://www.chiphell.com/thread-2183951-1-1.html (google translate is needed). Discovery in short: the ping from core 0 to core 1-63 shows a 5-step stair (inside CCX -> connected to the same IOD...
- Gnyueh
- Post #3
- Feb 3, 2020
- Forum: CPUs and Overclocking
Question The IF interconnect topology inside sIOD of ROME?

It is very clear now from die shot that ROME's sIOD comsists from 4 slices of cIOD, but it remains much unclear that how these 4 slices are connected (ring or Xbar? or any other kind ) Does anybody have any idea on this?
- Gnyueh
- Thread
- Feb 2, 2020
- Replies: 13
- Forum: CPUs and Overclocking
Qualcomm has Snapdragon 8cx beating Core i5-8250U in PCMark 10

32bit MS cannot emulate x86-64 on ARMv8 for now. So you cannot run x86-64 apps on 8cx
- Gnyueh
- Post #11
- Aug 16, 2019
- Forum: CPUs and Overclocking
AMD Ryzen 3000 Builders Thread

I wonder if there is a PCIe Brigde (or so call PLX) that can transfer 4.0 * 4 to 3.0 * 8, i searched and only found some PCIe 3.0 bridge.
- Gnyueh
- Post #54
- May 29, 2019
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

15% int is far too optimistic
- Gnyueh
- Post #2,785
- May 20, 2019
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

thanks,,,,
- Gnyueh
- Post #2,774
- May 19, 2019
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

I just noticed optimization to uop cache,,,, thanks
- Gnyueh
- Post #2,773
- May 19, 2019
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

i cannot really find a video about new i cache design, could you please share it? probably not now because showing off all your power at once even before your enemy reacts is not a wise choice
- Gnyueh
- Post #2,769
- May 19, 2019
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

i realized there's nothing valuable other than 48M L3cache indicating there is 3CCX fully enabled and i am afraid that my post will make that guy who shared that pict get punished
- Gnyueh
- Post #2,768
- May 19, 2019
- Forum: CPUs and Overclocking

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