Great part of the single-thread IPC increase is coming from 32 MiB instead of 16 MiB of cache being available to single thread.
But when running heavily multi-threaded software, there are now 8 cores, 16 threads competing from this same 32 MiB of cache, instead of 4 cores, 8 threads competing...
The only bullshit are stupid complains about it from people who don't understand that memory chips come at sizes of power-of-two or what it means to total memory capacity.
Its not just "possible", its how EVERYTHING has been done for the last 25 years.
SRAM(cache) is about 4 times more dense than logic in average. And there is also big difference between logic made to be fast and logic made to be dense. Comparing transistor counts do not make much sense...
No, they could not.
eDRAM scales badly with new mfg processes and is not supported by TMSCs "7nm" process at all.
Those IBMs chips wil eDRAM cache are made with old mfg processes.
SRAM scales very well with new processes and is only about 1mm2 per 1 MiB on TMSCs "7nm"
8 zen2 cores with ~13% ipc increase over zen1 and , ~4.8 GHz turbo clock and ~4.2 GHz base clock would give 9900k a good run for the money, typically losing slightly on single-thread performance but winning slightly on multi-threaded performance.
6-core CCX would increase L3 latency.
They are already making 338? mm² Vega 20 die
~150mm^2 ryzen die is not a problem for the TSMC "7nm" process in it's current state.
So they can easily also make ~150mm² 8-core desktop ryzen immediately, without any chiplets.
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