About as funny as the AMD fanbase accusing a AMD sponsored dev of taking bribes from Intel. If Alder Lake destroys Zen 3 by 40% in a AMD sponsored gaming benchmark, it would be hilarious and I would expect Intel to put it on their presentation.
You're assuming throwing more cores at driver submission threads always increases performance. We already see that 16T barely increases performance over 8T. 24 threads trying to queue could very well decrease performance relative to 16T or even 8T.
I really have to laugh at these two thinking AotS devs of all people are paid off by Intel.
Same versions, High_1440p preset, 12900K still 25-40% ahead depending batch levels.
3.0 vs 3.10, margin of error difference in CPU performance for a 5950X by doubling threads
3.0...
Easy. Gear 4 + CR2 which effectively means 1 command every 8 DDR cycles.
Like eek2121 says, flipping out over memory latency on a ES 0000 chip is pointless. Rocket Lake 3800CL16 is now hitting AIDA 40ns on Gear 1 after it was doing 50ns on launch firmware, never mind whatever it was hitting...
ComputerBase's CPU editor is livid for sure. He made a colorful post on their forum and the summary is he is not pleased about Anandtech deciding to bypass the NDA.
Tiger Lake H is going to clock on 5GHz on multiple cores, already confirmed.
Rocket Lake will be easier to cool than Comet Lake because the core is 20% bigger at the same max power levels.
The up to 19% claim is based on SPEC2017 ST based on their fine print.
It is a little wild how the same...
Power consumption is what ever is set in the motherboard firmware.
Efficiency is great compared to Skylake
11990K 143W for AVX2 FPU stress and 184W for AVX512 FPU stress.
9900K at 181W AVX2
Rocket Lake would have more 256-bit FPU resources so at 143W it would be beating the 181W 9900k in...
I don't know where you get your confidence from.
https://www.anandtech.com/show/14664/testing-intel-ice-lake-10nm/4
Skylake 8C desktop has 17% higher IPC over Skylake 4C laptop from double the cache and a desktop memory subsystem. This should clue you into the nature of the benchmarks you are...
I got a relative to run MLC on a TGL 1135G7 Inspiron laptop he got for school.
30ns HITM i5-1135G7 latency at 4.2GHz
My system for reference
22.5ns HITM 9900K at 5GHz/4.7GHz
The L2 <-> L2 latency hasn't increased much in relative cycles with the switch to non-inclusive.
Other notes:
14.5W...
I swear every time I visit this thread you guys substract a few 100Mhz and % IPC from Rocket Lake. Now it's just a refresh of Skylake?
Mebiuw still claims 18% IPC in Spec2017 over Comet Lake.
Which makes sense if the core is from Willow Cove bolted onto the Sunny Cove cache configuration.
Looks like it's capped at ~3GHz on Kraken and Speedometer. That's a straight up busted power management firmware. No reason why it should be doing worse than Ice Lake.
Power numbers in Windows from another reviewer
15W sustained vs 24W for the Ice Lake version is also baffling. The chassis...
The issue is the cost of single-thread performance doesn't scale linearly.
So given a particular transistor budget, a big array of small cores will beat out a small array big cores in nT tasks... like Cinebench.
It has new instructions, CET, and a major high-bandwidth cache redesign.
10SF is a metal stack change if their architecture day graphic is to go by. There are too many metal layers compared to the previously disclosed 10nm. It's practically a new process at that point.
Therefore even if the...
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