I estimated 250-300 mm^2 without L4. The actual die size suggest maybe there will be an L4 after all. But perhaps not a big one. Say 128-256MB. We can hope.
I got 420 mm^2 for the I/O and 72 for the CCX. Close enough. The edges are hard to discern.
May I use your pictures in case I need them for illustration in future?
Referring to the "AMD-style" version of the block diagram, you can see that I simply separated the CCX from the IF SDF Plane and put it on a separate die. The interface between the CCX and the SDF Plane remains the same as Naples. While not explicitly stated, I imagine it will run at MEMCLK, as...
Sorry guys, some how I can't embed the images and make them show up inside the post. Anybody wish to, please help me do that and delete the old posts. Thx.
One way is to use memory compression as I depicted in my diagram. 16 channels is not practical, imo. The pin-count will be too high and it will be very challenging to lay out the motherboard. Though a bit further out, the solution is DDR5.
L4 cache will useful in mitigating DRAM latency and bandwidth. But to be effective, it needs to be fairly large, something like 8MB/core or 512MB. At 14nm, the SC die size will be too large, so this is probably not going to happen. Moving to 8-core CCX and increasing the L3 cache on the CPU die...
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