leoneazzurro

Latest activity Postings Featured content About Trophies

• • L

    leoneazzurro replied to the thread Discussion RDNA4 + CDNA3 Architectures Thread.

    What I meant is that efficiency of an architecture is a thing, efficiency of a SKU is another, even if there is a dependence of the...

    Nov 14, 2024
  • L

    leoneazzurro replied to the thread Question Speculation: RDNA3 + CDNA2 Architectures Thread.

    7800M is Navi 32.

    Nov 12, 2024
  • L

    leoneazzurro replied to the thread Discussion RDNA4 + CDNA3 Architectures Thread.

    Just like current 4090M is more efficient than 4080M, you trade chip die size for performance. Efficiency of an architecture is...

    Nov 11, 2024
  • L

    leoneazzurro replied to the thread Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000).

    Some 14900 already did even before the 9800X3D reviews came out...

    Nov 7, 2024
  • L

    leoneazzurro replied to the thread Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads.

    Sometimes it becomes vinegar...

    Oct 8, 2024
  • L

    leoneazzurro reacted to Hans de Vries's post in the thread Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000) with Like.

    Zen 5 die: TSV's to the 64 MB X3D L3 cache: It simply must have enough and well distributed TSV's... It looks like a all the TSV's...

    Oct 8, 2024
  • L

    leoneazzurro reacted to MS_AT's post in the thread Discussion Zen 5 Architecture & Technical discussion with Like.

    Any data to back this up? Optimization manual doesn't talk about it, it's not included in any latency tables that I know of. And the way...

    Oct 8, 2024
  • L

    leoneazzurro reacted to Tuna-Fish's post in the thread Discussion Zen 5 Architecture & Technical discussion with Like.

    That's if you try to make wide permutes very low latency. I find that AMD's optimization manual for Zen5(zip, contains pdf and...

    Oct 8, 2024
  • L

    leoneazzurro reacted to naukkis's post in the thread Discussion Zen 5 Architecture & Technical discussion with Like.

    You can't slice AVX512 instructions efficiently. For being able to do fast 512 bit permutations register file needs to hold whole 512...

    Oct 8, 2024
  • L

    leoneazzurro replied to the thread Article State of RDNA era AMD.

    That's for sure, but Nvidia also has the same issue even if at a lower extent: its not that Ada and Turing work in the same way at low...

    Sep 17, 2024
  • L

    leoneazzurro replied to the thread Article State of RDNA era AMD.

    Yes to the first part but in any case hardware architecture and unified software are different things, you can have an unified stack...

    Sep 17, 2024
  • L

    leoneazzurro replied to the thread Article State of RDNA era AMD.

    You are comparing a graphic architecture with a programming environment. It makes no sense.

    Sep 17, 2024
  • L

    leoneazzurro replied to the thread Discussion Intel current and future Lakes & Rapids thread.

    They are but they are not exhaustive and the conclusion is missing many points.

    Sep 12, 2024
  • L

    leoneazzurro replied to the thread Discussion Intel current and future Lakes & Rapids thread.

    Playing games on workstation is plainly stupid. Period. A consumer CPU will do a better job for way less money. But, to be fair, the...

    Sep 12, 2024
  • L

    leoneazzurro reacted to Mahboi's post in the thread Discussion RDNA4 + CDNA3 Architectures Thread with Like.

    I am withholding every bit of faith until it's out. Intel claiming to go from barely usable ACM to BMG somehow diffing RDNA 3.5 seems...

    Sep 4, 2024

  Show older items
• Loading…
• Loading…
• Loading…
• Loading…