Ahh, the regular AMD hype train is getting started again.
I'm going to be cautiously but reservedly optimistic. The old slide with the "about 10+%" IP boost with likely modest clock increases is what I expect. Most of the uplift in light loaded ST scenarios, with MT getting hamstrung by...
GPU performance on tensor was not a priority. Stability and having a fixed validation target was higher on the list. I suspect that it'll be a while before they update again.
It's already there on the SoC. If it failed, then the chip isn't marketable to the west. If it didn't, then it keeps the product relevant for full featured Windows, which is still the biggest target market available.
Stuff with a failed NPU will likely just get sold overseas in secondary markets.
What I'm more interested in is if the next Gen game consoles get 3dCache? If their primary use case is exactly what that is targeted at, why not use it?
More than likely, AMD is getting more Xtors per $ with Samsung 4LPP than with TSMC N4C. We heard about AMD booking S4nm capacity about a year ago, many speculating that it was for a "Mendocino" like processor. As badly as Samsung is floundering, they are likely desperate for customers...
Even though RDNA4 offers improved memory utilization efficiency over RDNA3.5, it's not enough of an improvement over it to warrant responding silicon without increased memory bandwidth. The increased RT capabilities still need more bandwidth, and increasing iGPU throughput without matching it...
If you are doing HPC development or even doing workstation work using those same applications, a dual 3dCache Epyc 4XXX processor would be a notable improvement. CFD with OpenFoam and Embree ray Tracing are two notable areas that see improvements. That's not to say that the regular 3d cache...
Reading the article just makes it sounds like AVX 10.x is just the next revision to AVX-512 and not some whole new approach. I don't this absolutely requires everything in the 'mont cores to be fully 512bits as they can still use the doubled 256 approach that's been used in other solutions in...
It's too bad that AMD can't do Strix Point refresh on a more recent node. N3e should be a bit less expensive by then and with fin flex, they should be able to manage a decent clock speed improvement all around.
I vaguely remember from long ago that there were processors that had bios settings where you could turn cache prefetch on and off. It's been a minute, I've slept since then, and there may have been an alcohol or two in my system along the way, so that's about all I have at the moment.
In general, the miss rate on a last level cache halves as the size of the cache quadruples. For example, if your hit rate on a 512Kb cache was 90%, your miss rate would be 10%. If you doubled that cache twice, to 2 MB, you would improve the miss rate to 5% and the hit rate to 95%. It would...
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