naukkis

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    naukkis replied to the thread Discussion Apple Silicon SoC thread.

    M4 has stronger cores so getting best performance and performance/watt happening point ain't driving all cores to max temp but instead...

    Saturday at 2:47 AM
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    naukkis replied to the thread Discussion RISC V Latest Developments Discussion [No Politics].

    Yeah I have missed that they have done split register file design. Didn't find yet information whether they support register-register...

    Mar 19, 2025
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    naukkis replied to the thread Discussion Apple Silicon SoC thread.

    In that is case Intel got its hybrid scheme wrong - they only need one big core for ST and as many as possible small cores for best...

    Mar 10, 2025
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    naukkis replied to the thread Discussion Apple Silicon SoC thread.

    Multithreading is actually getting best performance out of process. GB6 has MT test. GB5 and Spec doesn't even try to measure...

    Mar 8, 2025
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    naukkis replied to the thread Discussion Apple Silicon SoC thread.

    Do you see MT score is a bit higher than ST? That's how those workloads will scale to MT. For most use cases MT performance measured by...

    Mar 7, 2025
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    naukkis replied to the thread Discussion RISC V Latest Developments Discussion [No Politics].

    I have questioned why nobody haven't do clustered execution cpu design. Last commercial one, Alpha 21264 Keller was part of design team...

    Mar 3, 2025
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    naukkis replied to the thread Discussion RISC V Latest Developments Discussion [No Politics].

    So Callandor will be clustered design with shared register file. Something very Keller like design from past, which I might have...

    Mar 3, 2025
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    naukkis replied to the thread Discussion ARM Cortex/Neoverse IP + SoCs (no custom cores) Discussion.

    That's a bit of wishful thinking. SVE shows it's SIMD-registers to software so it's length has to be defined for hardware - and for...

    Mar 1, 2025
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    naukkis replied to the thread Discussion ARM Cortex/Neoverse IP + SoCs (no custom cores) Discussion.

    It is Apple design - firstly known as AMX. Arm implemented it later to their instruction set. It's a subset of SVE - you know your...

    Feb 25, 2025
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    naukkis replied to the thread Discussion ARM Cortex/Neoverse IP + SoCs (no custom cores) Discussion.

    What Apple did - they took those vector length agnostic parts from SVE, added few outer matrix registers for better supporting matrix...

    Feb 25, 2025
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    naukkis replied to the thread Discussion ARM Cortex/Neoverse IP + SoCs (no custom cores) Discussion.

    It's about vector length agnostic designs - there is full vector isa implementations and ARM SVE, scalable packed SIMD arch. And ARM...

    Feb 22, 2025
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    naukkis replied to the thread Discussion ARM Cortex/Neoverse IP + SoCs (no custom cores) Discussion.

    Vector ISA is hardware abstraction layer. By definition everything just works - and it's not only theoretical as working vector cpus...

    Feb 15, 2025
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    naukkis replied to the thread Discussion ARM Cortex/Neoverse IP + SoCs (no custom cores) Discussion.

    I don't understand why? RVV is vector isa, pure and clean. SVE instead is scalable packed SIMD - which doesn't actually work beyond...

    Feb 15, 2025
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    naukkis replied to the thread Discussion ARM Cortex/Neoverse IP + SoCs (no custom cores) Discussion.

    Hardware can easily detect data patterns from runtime execution which cannot predict in compile time. When it detects those and those...

    Feb 15, 2025
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    naukkis replied to the thread Discussion ARM Cortex/Neoverse IP + SoCs (no custom cores) Discussion.

    Vector cpus vectors are independent scalar ops. Vector cpu''s can usually chain those ops between execution units and if data addresses...

    Feb 15, 2025

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