The physical problems are the same, this is just an engineering/accounting tradeoff between RMA rates and performance. Now that AMD provides effective competition again, delivering optimal performance for the top mainstream SKUs has become a higher priority than minimizing RMA rates, because...
If you want to use low buffer depths (64 or 128 samples), stay away from Ryzen/Threadripper. They handle low-latency DAW processing very badly. See the TechReport reviews here and here, as well as the articles from ScanProAudio here and here. If you are using higher buffer depths, the AMD...
There really wasn't an option to keeping core counts stable, as long as AMD refused to compete. AMDs CPUs have been so noncompetitive, if Intel had increased core counts at fixed price points for their mainstream SKUs, AMDs CPU sales would have pretty much stopped. If Intel had done that with...
For 14nm, the wafer cycle time alone is around 90 days; then the wafers need to be shipped to the packaging plant where they are cut into dies, tested/binned and packaged. Then the CPUs are shipped to the distributors, which then ship to retailers. So that's probably closer to 4 months between...
No, that sounds right. SIMD=Single Instruction Multiple Data, i.e. a single instruction will perform several arithmetic operations at once, in contrast to scalar code, where one instruction performs a single arithmetic operation. Thus SIMD code needs fewer instructions to perform the same number...
The discussion about the number of ALUs misses an important point: ALUs don't matter if you can't keep them fed. For that you need a sufficient number of Load/Store Units. Zen will retain the two LSUs from the Bulldozer family. This will probably pose a pretty hard limit on the performance of...
That will be IBMs SOI-based 14nm FinFET, which GF only acquired in 2014 together with IBMs foundry business, far too late to be used in Zens design. GF may also be contractually obliged to not offer this process to other customers, or only offer it well after POWER9 launches.
IBM has been using...
Kumar didn't say it "will take" 12-14 months, but that it "can take" 12-14 months. And that's easily possible; depends on bugs detected during silicon validation and any possible respins necessary to get parametric yields to acceptable levels. Remember that Broadwell production silicon was on...
Cost shouldn't be much of an issue in this case. The smallest BDW-EP die is probably 10c (smallest HSW-EP die is 8c). With the 14nm shrink, the BDW 10c should be quite a bit smaller than HSW 8c. Most sales will be for 6c/8c, so Intel won't need too many fully functional 10c dies. Even with the...
Where did AMD talk about performance? AFAIK they only talked about IPC (which is completely meaningless without a frequency/performance target). Personally, I think +40% IPC @"we're not telling" GHz is completely believable.
The problem is not disk or CPU, the load values are far too low for that.
Modern HDs will deliver ~100 MiB/s, and DAWs will pre-buffer during playback, so you won't get I/O problems until you're playing back many many more channels. And you're not even fully using one CPU core in this case, so...
AMDs market share in 2Q14 was:
x86 overall, counting consoles: 16.3%
x86 overall, without consoles: 11.2%.
x86 segments: console=100%, DT=15.0%, mobile=9.6%, server=2.2%.
I doubt they managed to double their DT market share in the last quarter with their anemic offerings, so there's no way for...
The 15ms (actually 15.625ms) resolution is not really a problem of the underlying timer hardware, but of Windows kernels. At least up to Win7, the "master tick" of the kernel runs at this speed of 1/64s. Many of the timer functions in Windows run off this master clock. You can check out the...
True for lower-end consumer boards but not for server/HEDT and probably the higher-end Skylake DT boards. It will be possible to use several DDR4 LRDIMMs on one channel. These Load Reduced DIMMs use active buffering so that they have bus load characteristics of a single DIMM even when multiple...
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