It's better than no tape-outs, but Intel's manufacturing track record makes this news less meaningful. Intel failed a lot due to an overly ambitious 10nm(which is 7nm now). They used new metal materials, new contact schemes(COAG)...etc and it failed. Intel 20A is quite ambitious as well since...
It simply points out that Intel had no choice but to use a higher voltage than what Raptor Lake used. We 'could' try undervolting, but we can't be sure that it won't break any critical functionality of the chip. Reliability, data integrity, CPU operation in certain high-demand situations...etc
Even if we put all these things into account, 3495X is still a huge disappointment. Their workstation counterpart, 5995WX also has 8 channels MC, and 128 PCIe lanes. 3495X was supposed to win 5995WX in legacy programs and roflstomp 5995WX in simulation and AI applications. But they're even...
I think they messed up much more than that. C23 doesn't need core-to-core communication, so it should work if cores are well-fed by memories. But its performance is practically on par with 13900K(with uses dual channels + 16 E cores).
It looks AMD CMT processors with additional Inter-core resources to me. Will it really perform well in ST workloads compared to vanilla BF OOO cores? I agree if they are planning to mitigate ST degradation due to small core sizes, but not sure if it's really the way to boost ST performances.
Oh..not really. It's true that Intel Cove team's pretty much screwed up, but you can't make hypothetical 1+0 BF Core who wins both latency and throughput against hoards of small cores. If GPU works, then why not E cores? Even if their P core team finds their way, E core will still be there.
AMD is introducing Zen 4c to fight computing densities. Either AMD's using simliar designs or not is not really important for customers. They're aiming for the same market.
Even today, hypothetical Saphhire rapids-sized chip with Gracemont will pack up 180 cores (Assuming 3 GM cores per 1 GC...
Probably not really useful even if they pack up more cores. They made AVX powerhouse with enhanced Golden Cove cores but still have 8 memory channels. Awkward times indeed...
Intel's dual-issue AVX512 indeed has its uses and shows us performance improvements. But that strength is somehow diluted by a lack of memory channel, so the true potential of AVX512 will be visible on HBM variants. This is somehow due to tile designs since you cannot scram 3 memory channels and...
Because photoresists can be applied only in a 'whole wafer' manner. As for incomplete edge chips, that's really up to manufacturers. There can be uniformity issues during etching and deposition processes if there are no adjacent logics.
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