Sorry if inappropriate
AMD said pipeline balancing in RDNA2, does this involve reduction of latency via reorganization of the VGPRs and scalar registers, and wave size (16 <- 20) or the wavefronts across SIMDs?
Earlier reports indicated that the shaders would traverse the BVH and the...
The SRAM will scale down alot in the transition to the 5nm
The relatively small bus will help with laptop inclusion, APUs will benefit from internal memory bandwidth issues
It'll help alleviate bandwidth constraints with future multi-application/multi-gpu processing, RT-related requests
And...
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