- Mar 3, 2017
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You're trying to boil down CPU performance factors to a single metric.My theory is that Zen benefits greatly from the schedule and execution ports, separate for the FPU and separate for the ALU.
You must understand, that despite of his nickname, he's devoted Intel user with a rather strange fetish for numbers.You're trying to boil down CPU performance factors to a single metric.
That's really-really not how it works!
Yeah but he's trying to model CPU perf in the most in(s)ane way possible.You must understand, that despite of his nickname, he's devoted Intel fan with a rather strange fetish for numbers.
This is one of many factors and I am not saying it is the most important one.You're trying to boil down CPU performance factors to a single metric.
That's really-really not how it works!
It's not really one relevant to Zen5 at all.This is one of many factors and I am not saying it is the most important one.
You. Just don't.This is the only way to find out and compare with Zen because LionCove separates the FPU ports from the ALU ports.
These are just two examples of online gaming among many applications and loads.It's not really one relevant to Zen5 at all.
You can just find the C&C article where Clam profiled 7950X in vidya to see the key back-end issues.
View attachment 98662
You. Just don't.
Most client workloads are like gaming: horribly front-end bound, and when they're not, throw ROB slots at it.These are just two examples of online gaming among many applications and loads.
So you're saying that AMD added 2 ALUs to Zen 5 for no reason, because 4 ALUs in Zen4 is not a limitation?Most client workloads are like gaming: horribly front-end bound, and when they're not, throw ROB slots at it.
Like, this is why MTL is an IPC regression in client w/l's. Same core, same boundaries, worse memory setup!
Smarter people already did the profiling for you. All you gotta do is read the charts. Not that hard.
well there gotta be some.So you're saying that AMD added 2 ALUs to Zen 5 for no reason
Not the main one, no.because 4 ALUs in Zen4 is not a limitation?
AMD must consider the entire spectrum of workloads, not just games. Zen5 is designed not only for consumer computers, but also for Epyc.well there gotta be some.
Not the main one, no.
Consult the chart.
Thank you for stating the obvious and not reading what I've said before.AMD must consider the entire spectrum of workloads, not just games
It's designed for client and cloud (and so is Zen6), these kinda share workload footprints, a lot being membound JITs and all.Zen5 is designed not only for consumer computers, but also for Epyc.
Pay me and I'll do it.Are there examples of profiling for other workloads/applications?
Just for context , Zen 4 was ~10-12% uplift with some minor tweaks versus Zen 3. If Zen 5 ends up being just 10-15% faster at iso clocks versus Zen 4*, then something went wrong in the design process. AMD has such advanced internal performance modeling tools that I find it impossible they would waste so much time and money to get so little out of it.
why.I still see very little reason to believe a 30-40% IPC uplift from either side (let alone more) is at all realistic in 2024.
ARLs are worthless memeparts.I think Arrow Lake's going to be quite disappointing as well
Well, a 5-10% IPC gain with clock regression is not at all surprising if I'll be honest. Just making the core wider and increasing total throughput, which appears to be what AMD has done, is actually a hilariously inefficient way to increase IPC on x86 due to register dependencies and memory/cache bottlenecks.
People forget that Moore's law was taken out behind the barn and shot about a decade ago.
Ain't happening till CFETs.If anyone figures out a new SRAM design that allows for greater density
I've said Chips and Cheese didn't I?Did you make this picture you pasted yourself or did you get it from somewhere?
Correct. I missed, or rather did not associate, the C&C abbreviation.I've said Chips and Cheese didn't I?
Do we know exactly what RoyalCore was supposed to be?I still see very little reason to believe a 30-40% IPC uplift from either side (let alone more) is at all realistic in 2024.
To clear the air about my supposed partisan allegiance: I think Arrow Lake's going to be quite disappointing as well, and already called out Royal Core as essentially being Bulldozer with more money thrown at it.
Enjoy the tears of disappointment and rage of everyone in this thread I will.
Clearly that stands for Command & Conquer.Correct. I missed, or rather did not associate, the C&C abbreviation.
Who cares.It has been suggested (Exist50) that RoyalCore and LionCove may be the same project
RIP my dear bestie.Clearly that stands for Command & Conquer.
why.
ARLs are worthless memeparts.
Only LNL exists.
Yeah it's not hard, but GB6 is worthless now since you can pump matrix matth subtest with shared accelerators.Any predictions if Zen 5 can match Apple M4 Geekbench 6 score that has been posted, in single thread? They seem to be continuously fudging Geekbanch 6, so not my favorite, but here it is anyway:
It doesn't.Only if it has AMX.
Does anyone know?
Maybe you don't care but I'm curious.Who cares.
None of that is relevant to Intel's current IP roadmap.