That was the goal but there’s 2 snags.
1) MTL was late. It was supposed to launch shortly after Phoenix.
2) ARL reuses MTL packaging. All of the negatives of that cursed tiled setup is inherited by ARL. The only kind of saving grace is that ARL-S has an SoC tile that’s more favorable to desktop but It’s still less than ideal.
Meteorlake was supposed to launch instead of Raptorlake. That is 2022! The timeline you are thinking about(H1 2023) is the
delayed version.
It may not be the most optimal, but there's still plenty of chances and low-level details they can make that'll improve the "cursed tile" issue as you and others are calling it. Idea is important, but it's also very important to successfully execute on that idea, since in theory, Foveros and tiles are supposed to be superior over the approach AMD uses.
Go back on some earlier Meteorlake slides. Making the losses of moving to Tiles irrelevant was their goal. They definitely missed many of the low-level targets they were originally planning.
True but you have to include packaging cost. Yields? Intel7 must be yielding insanely good the last years so MTL didn't help with yields. Maybe it even resulted to worse yields since Intel4 is a newer node.
There are three types of yields:
1. How many dies you can get out of the wafer? A 100mm2 die allows you to make more than double the 200mm2 dies, because a larger die has more of the portion of the wafers lost. This is assuming zero silicon defects.
2. Does it have defects on silicon? Defects on silicon(which are random) can further reduce the amount of dies you can get out of the wafer. While Intel 7 may be mature and have extremely low silicon defect rate, the die being bigger means you have more of the wafers being wasted. Smaller dies also have less chance of a defect disabling a critical portion that renders it useless compared to a larger one.
3. Parametric yield: Cannonlake may have had low silicon-level defect but it's not enough. You need to have it perform. The parametrics, or the performance of the silicon matters. What would you take? A 10% faster one with 20% defects or one without the defects but without the 10% advantage? The 10% advantage can easily make up for the silicon loss by allowing it to be sold for higher cost.
Do not overestimate the cost of the silicon. For small die parts such as Intel's Core i3 and below line, the costs of the packaging is similar to the cost of the die. It was something like $5+$5. So in such a case, it's not really advantageous to get to a smaller die, because it's a small portion of the total cost.