Some of this may become clear after we see the V/F curve and Cac weights for the coresMaybe in a couple years, if AMD really was expecting bigger jumps from Zen 5, we will get the whole story from a couple of engineers who worked on it.
/s of course (MLID just got lucky here) but still lol
oh its over for the DDR5 5600 peopleGot this from Olrak on Xitter. Looks like the gaming comparison was made using 6000 MT/s DDR5 for both Zen 5 and the 14900KS. The Intel mobo was set to "Intel Defaults", but I'm not entirely sure what that means these days.
View attachment 100288
No it's the actual CDNA4.
Different stuff to support way different speeds and feeds.
That one moves the paradigm into a different direction.
Used to be called MI500.
I don't think the point of contention here is about how much larger the CCDs are, just how much larger the cores are
Yea.Mi400 should coincide with HBM 4 in 2026.
Iirc that's just an option for HBM4.Since HBM4 will be SoIC stack
So basically all computing devices: FlopArrow Lake: Flop
Zen5: Flop
Apple M4: Flop
Cortex-X5: ? (Flop, obviously, we know how this story ends)
I read that as last day of July and same MSRPs.Weird that no pricing info was released for Ryzen 9000 and no release date.
So basically all computing devices: Flop
Back to the the slide rule or abacus I suppose.
1700X -> 3700X -> 5800X3D for me. Would have skipped zen 2, but at some point it looked to be the end of the road for B350I did 3800X - 5800X - 5800X3D
No it's the actual CDNA4.
Different stuff to support way different speeds and feeds.
That one moves the paradigm into a different direction.
Used to be called MI500.
Why ask someone just caught red handed lying to everyone for the last year?There were some rumors that the next version (presumably CDNA4) would reshuffle the die sizes, moving to fewer and bigger dies.
If that's part of the plan, would that be part of the Mi350 (using the current naming) or one after that, Mi400?
Yeah packaging yield is a concern so less dies balances the net yield. Wafers are plentiful relative to adv packaging.There were some rumors that the next version (presumably CDNA4) would reshuffle the die sizes, moving to fewer and bigger dies.
If that's part of the plan, would that be part of the Mi350 (using the current naming) or one after that, Mi400?
Based on that trend, whatever comes after Zen 6 is gonna have like 5% IPC increase and then after that 0% IPC uplift.View attachment 100290
This slide was spot on, seems Zen 6 with 10% IPC would be what I would bet on.
MLID the winning leaker.
AMD took almost two years for a paltry 16% while Apple and ARM iterating on almost yearly cadence.
It's not even that, just that tracking so many L2 instances is hard.Yeah packaging yield is a concern so less dies balances the net yield
No need of sources for thatI have a super duper reliable source that says 9950x MSRP is $1000.
Not an MLID slide. I was the one that convinced Adored not to do a video on it, because the IPC number was lower than expected. My fault for accidentally giving MLID more credibility.And yet your proclaimed +32% has been proven to be wrong, and the MLID slide's "10-15%+" has been proven to be right.
What are you actually arguing here?