There are many questions floating in my head.
- completely new grounds-up design in development since 2018
- designer's dream
- magic frontend
- so much more resources, width, and depth
- finally a GLC level resources
- Zen 4 was anemic
- Zen 3 was a similar grounds-up design - but just reshuffling the components
- 100% op-sec - Osborning the entire lineup
- MLID got fake slides - disregard 10-15%
- 32-40% 1T
AMD's performance reveals have been a mess a few different times now. Just strange errors, sloppy work and confusing all around."AMD Performance Labs" is such a joke. They have only succeeded in confusing us. I wonder if they came up with honest results and then marketing told them, no no. We want it like so and then they were forced to create the jumbled up mess that we got.
I think it's obvious that the original goal was much more ambitious. One thing is the hypetrain and house numbers like a 30% better ipc and such nonsenses .. the second thing is that when you do ground up redesign with increase the number of ALU´s by 50%, the frontend doubles and intergenerationally huge increase the number of transistors, you don´t do it because of 16% IPC..... Zen2 had 15% with cosmetic changes, Zen4 had 13% and that was not an architecture focused primarily on ipc but on clocks and avx512.. I really don't believe they aimed below 20-25%. . it also confirms that for ZEN 6, which was supposed to be just an evolution, they will eventually completely redo the frontend.There are many questions floating in my head.
- completely new grounds-up design in development since 2018
- designer's dream
- magic frontend
- so much more resources, width, and depth
- finally a GLC level resources
- Zen 4 was anemic
- Zen 3 was a similar grounds-up design - but just reshuffling the components
- 100% op-sec - Osborning the entire lineup
- MLID got fake slides - disregard 10-15%
- 32-40% 1T
I think it's obvious that the original goal was much more ambitious. One thing is the hypetrain and house numbers like a 30% better ipc and such nonsenses .. the second thing is that when you do ground up redesign with increase the number of ALU´s by 50%, the frontend doubles and intergenerationally huge increase the number of transistors, you don´t do it because of 16% IPC..... Zen2 had 15% with cosmetic changes, Zen4 had 14% and that was not an architecture focused primarily on ipc but on clocks and avx512.. I really don't believe they aimed below 20-25%. . it also confirms that for ZEN 6, which was supposed to be just an evolution, they will eventually completely redo the frontend.
Perhaps this will make more sense when Turin is officially launchedWell it makes sense to list them as it was the way they did it in the past. Zen 4 had a bigger SMT uplift (34% vs 25%) so it makes sense to list 1T and use same core count parts when doing the IPC comparison.
Only Mercedes used to sandbag, and that too at the height of their domination in F1.That leads me to believe that AMD is sandbagging Zen 5 max performance
Not sure I'm following, sorry.It may be useful for separating the core potential from the thermal and power limitations.
1T scores aren't power- (and rarely thermally-limited), nT scores are.Not sure I'm following, sorry.
Could be because they are unsure of what Arrow Lake may be like. Zen 5 may be winning a lot of benchmarks in July against 14900K/KS (even by 1%) but AMD would prefer supremacy so they may have something in store for the Arrow Lake launch (optimized AGESA, new models with boosted clocks, high speed EXPO kits etc). There's also the possibility that the Zen5X3D by year end may be based on 3nm silicon and so may boost to 5.7 GHz at lower power, heat and voltage without harming the V-cache die. As of now, the situation just seems too muddy.Besides, what is the point of sandbagging something like CPU performance?
We have, but you're not gonna like the info, AMD is hellbent on having errors in all of their important slides/end-notes. How they managed to write GB 1T in the slide and GB multi-core in the end-note is anyone's guess.we have one look at 1t using GB6 3.0. HX 370 up to 5.1GHz vs X Elite up to 4.2GHz?.
Do we have endnotes for this slide?
I was asking what's the need in these 1T scores in IPC "geomean" for desktop parts, not what they are.1T scores aren't power- (and rarely thermally-limited), nT scores are.
Not all workloads are power- and thermally-limited, so nT scores are a poor proxy to estimate gains in those.I was asking what's the need in these 1T scores in IPC "geomean" for desktop parts, not what they are.
That. And, in addition, it could be useful to see the improvement at core/cache level, instead of at SKU level.Not all workloads are power- and thermally-limited, so nT scores are a poor proxy to estimate gains in those.
That's ok, it means the products will be affordable.In retrospect of the Zen 5 launch, it is clear that some compromises were made to keep the die size to minimum.
Well obviously. That's for the perfectly balanced 50% margins (50% expenses / 50% profits for AMD)