I have so many thoughts on the Clark interview now. IIRC it was in 2021. Did they still hope to make Z5 on 3nm back then?I'm wondering if Mike Clarks comments were made before the realisation that intel would go HAM with power usage, forcing AMD to increase Zen4 more than the average user wanted/liked. Zen5 is decent in laptops, and in server... ie at "reasonable" power limits. Without Zen4 being pushed to 170W already, Zen5 (@ say, 140-150W) may have been on track to be better positioned using previous power/perf estimates.
that’s a good lead to have against Intel. ARL isn’t due till Q4 2024. So Strix will go against Meteor Lake for 5 months.
Very likely. It's around the same time Intel signed up for the original N3 node, before the issues arised.I have so many thoughts on the Clark interview now. IIRC it was in 2021. Did they still hope to make Z5 on 3nm back then?
That's a bit above M3 Max MBP performance with its 12 P + 4 E cores.
People asked about Zen 5 power efficiency.
In fact, the initial impression is that gaming may be one strong point about Zen5, while other applications may be more sensible to the power used.Most gaming workloads have no power/thermal limitations.
I understand your interest in ST scores, but for me personally the presented geomean IPC breakdown is enough.
There's also the possibility that the Zen5X3D by year end may be based on 3nm silicon and so may boost to 5.7 GHz at lower power, heat and voltage without harming the V-cache die.
If memory traces will stay the same as before, 600 and 800 will have the same memory support on similar CPUs. But, If they're differrent, then... they're differentI've seen all kinds of speculation on this, I thought memory speed support was like 90% the controller in the CPU?
Haha...I think a lot of the hype was too much focus on AVX 512 gains and integer gains. It seems you always need more drastic cache structure changes to get huge IPC gains in myriad of workloads...but I didn't see any leaks of any kind suggesting that...so I always assumed a lot of the "gamer" community might be disappointed. But I am still waiting for the more "mobile"/"efficiency" testing of strix vs all the competetion to see how good/bad zen 5 is. The release of Strix Point with Granite Ridge on it's own is very significant change in focus and I am sure Zen 5 cores themselves were designed more to maximise Strix point than Granite ridge. And it seems all the "geekbench" and similar focus of stuff that gets compared to ARM will be pretty big gains, while power efficiency might be also for a minor node shrink and still being a node behind some ARM designs. Seemingly Zen 6 is the generation that addresses all the more chiplet derived products more than this anyway.Are you suggesting that I intentionally overhyped Zen5? Are you brain damaged?
I have so many thoughts on the Clark interview now. IIRC it was in 2021. Did they still hope to make Z5 on 3nm back then?
First of all, I really doubt it can do 2400 fclk. Also, in reality, you don't need expensive boards and RAM, just get something that works with HV less half-donkey-ed like my Gigabyte board does, and get one of Kingbank $100-150 hynix 24gbit/16gbit a-die kits that can easily do 8000+ with good timings.may have to get expensive EXPO kits and a decent X870 mobo minimum to make the most of their Zen 5 upgrade.
I think even low-end Asus 2DPC boards can easily do 7600 ish MT/s with one stick per channel, other brands (gbt/msi/asrock) can go even higher in general practice. It's all moot if IF is the same, which is the most probable outcome, I guess.I've seen all kinds of speculation on this, I thought memory speed support was like 90% the controller in the CPU? Certainly overclockers are getting 8000+ on X670E boards today? It would really suck if the current high end boards can't handle a modest 'sweet spot' DDR5 increase to 6400/6800/7200, when the X870 chipset has the exact same hardware.
“IPC” depends on the workload, and I think it would be good to discuss it as such. Looking at GB6 subtests, M4 improved iso-clock performance between 0% and 30% (this is discarding tests that benefit from the new matrix hardware). In the few sub tests where the iso-performance did not improve (most notably, Clang), Apple already leads the industry by 50-60% iso-clock, so this is the area where improvements are most hard to come by.
my goodness. The level of defence for AMD. ARM did 16% YoY. 16% in 2 years and a "new" core is not good. Its average.
Apple is stuck atm, we know that.
It doubled per software estimated methods but in platform power (from USB) idle normalized I don’t think it doubled, but that’s also because people underestimate M1/2/3 power since they rely on powermetrics too much. By phone methods or AC minus idle you’re looking at 5.5-9W throughout the range, and more like 8-9W with M3 I think. You’re looking at like 11W with the M4 from one iPad test, and because some of the other stuff from RAM and power delivery is different and similar or even reduced thanks to LPDDR5x that helps. But I could believe core power alone doubled.Yes, but the power consumption of M4 has more than doubled compared to M1.
I agree here. The iso-clock power gain is like 5% over the M3 so they’re not going to be able to do much MT gain other than by pushing power or by more E Cores.One P-core in M4 running at 4.5 GHz consumes 7.2 to 9W. If you have 12 of them (in M4 Max), the total power consumption only for the CPU part will be nearly 100W.
Roughly speaking yeah something like this.Apple has to throttle them down back to M3 levels. As a result, the performance of M4 Max will be nearly the same as that of M3 Max on MT load.
Of course, but the generally accepted IPC comparison has been SPECint for a while now.
Bruh?Where are you getting 16% IPC increase for ARM Y/Y?
Well, from what I read its supposed to be twice as fast. We will see when benchmarks hit.Didn't really follow all the debate here; any info on AVX512 implementation? Can it do 2x AVX512 / cycle? Doubled load bandwidth seems to indicate, it can load 2x512 bit, which is on par with Golden Cove.
Yes, I don't know where some comments come from. lack of knowledge I think.This is hilarious to watch.
Do none of you remember the slow creep up of IPC from Sandy Bridge to Skylake, and the complete stagnation after that for years? 15% increase is fine, good grief.
What a bean counter, no competition, cpu. Cache starved to death, cheap process. What a disappointment.
Didn't really follow all the debate here; any info on AVX512 implementation? Can it do 2x AVX512 / cycle? Doubled load bandwidth seems to indicate it can load 2x512 bit, which is on par with Golden Cove.
N4P is anything but cheap.
AT confirmed that it is 2x512-bit now. That might be where the bulk of the transistors went (ie: AI)
A 12 Core part is obviously more efficient than an 8 Core part, because the load is distributed over a higher number of Cores which can clock lower. So you can't take this and say "ZEN5 is x% more efficient than ZEN4. We need to wait for July 30th when 3rd party Reviews should drop.People asked about Zen 5 power efficiency.