Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

H433x0n · Jun 4, 2024

gdansk said:
Watch me I can grab a screen shot from TechPowerUp review too

Looks like Arrow Lake with 15% more IPC at 5.7GHz will still be behind the 7950X that's weird...

That’s multicore performance. Not the topic of conversation.

coercitiv · Jun 4, 2024

H433x0n said:
That doesn’t affect 1T performance.

1T performance can be affected in non-Intel defaults BIOS by disabling TVB and undervolting, allowing max boost even when a core is past the temperature threshold (and using lower voltage)

Let's not derail this thread right after we got juicy info on both Lion Cove and Skymont please.

coercitiv · Jun 4, 2024

Lion Cove is looking ok, Skymont is looking great. What matters now is clocks and power to get there.

HurleyBird · Jun 4, 2024

Skymont looks awesome. But for Lion Cove, Intel's SMT yield was, what, ~25% or so? Maybe a bit less? Still, unless there's a big improvement somewhere else like area, seems a bit "one step forward, two steps back," does it not?

H433x0n · Jun 4, 2024

coercitiv said:
1T performance can be affected in non-Intel defaults BIOS by disabling TVB and undervolting, allowing max boost even when a core is past the temperature threshold (and using lower voltage)

Let's not derail this thread right after we got juicy info on both Lion Cove and Skymont please.

Huh? That’s jumping through quite a few hoops there.

If the last gen part has to have TVB disabled for AMD’s next gen Zen 5 to get a win in 1T performance that’s not really a gotcha.

HurleyBird · Jun 4, 2024

H433x0n said:
We don’t even know if ARL-S doesn’t have HT, there were hints that may not be the case anymore.

Interesting. Hints from where?

tamz_msc · Jun 4, 2024

HurleyBird said:
And Intel's aren't?

Smart money is that a small fudge factor exists for both.

Which means IPC is likely to be close enough that the winner comes down to benchmark selection more than anything.

AMD of course should win by a significant margin if we shift from 1t IPC to 1c IPC, with the deletion of hyperthreading.

The two big questions are how badly that deletion hurts Intel, and how well Lion Cove clocks.

Since I haven't seen any mention of AVX512 yet, I'm assuming it's still a no show for consumer chips?

Intel's are less likely to be fudged because they are transparent on the OS, compiler, and benchmark used, while mentioning them in the slide, and not in the end-notes.

As for SMT or lack thereof, it's insignificant.

vanplayer · Jun 4, 2024

gdansk said:
Lunar Lake is the only one rumored to have a fanless option so the choice is pretty much made for me. I think it'll be good enough to replace my M1 MBA (if it exists).

You mentioned fan/fanless.
From all what I know, fanless option would be hard to clock as high as M4. It's either x86 or N3B problem, maybe both.

H433x0n · Jun 4, 2024

HurleyBird said:
Interesting. Hints from where?

It doesn’t appear that the LNC in ARL-S will be the variant that has HT support physically removed from the core. Whether or not it gets toggled on before release remains to be seen.

gdansk · Jun 4, 2024

vanplayer said:
You mentioned fan/fanless.
From all what I know, fanless option would be hard to clock as high as M4. It's either x86 or N3B problem, maybe both.

It just needs to clock higher for long enough to run Speedometer 3.0 without throttling

HurleyBird · Jun 4, 2024

tamz_msc said:
Intel's are less likely to be fudged because they are transparent on the OS, compiler, and benchmark used, while mentioning them in the slide, and not in the end-notes.

Literal cheating isn't the issue. There's no need for it. You fudge by being selective with the tests that contribute to the geomean.

tamz_msc said:
As for SMT or lack thereof, it's insignificant.

And those charts support that assertion... how?

HurleyBird · Jun 4, 2024

H433x0n said:
It doesn’t appear that the LNC in ARL-S will be the variant that has HT support physically removed from the core. Whether or not it gets toggled on before release remains to be seen.

But what's the source/s for all this?

ondma · Jun 4, 2024

H433x0n said:
How the tables have turned. If those clocks are real Zen 5 is cooked in 1T and nT performance. It’s best bet is gaming assuming IOSF latency is as bad as predicted.

GG, better luck next time.

Seriously? This thread is getting way ahead of itself. I thought I saw leaks that Zen 5 will have similar clocks, and dont forget ARL is giving up hyperthreading, so the E cores better be really good. ARL will still have to have a really good IPC increase for the P cores to beat Zen 5.

H433x0n · Jun 4, 2024

HurleyBird said:
Literal cheating isn't the issue. There's no need for it. You fudge by being selective with the tests that contribute to the geomean.

Using random GB5 sub tests isn’t being selective to fudge the geomean?

H433x0n · Jun 4, 2024

HurleyBird said:
But what's the source/s for all this?

None, feel free to disregard it. It’s highly likely that ARL-S has HT disabled in production.

tamz_msc · Jun 4, 2024

HurleyBird said:
Literal cheating isn't the issue. There's no need for it. You fudge by being selective with the tests that contribute to the geomean.

And those charts support that assertion... how?

SMT is irrelevant for ST, only relevant for MT in workloads like rendering which aren't done on the CPU anyways.

HurleyBird · Jun 4, 2024

H433x0n said:
Using random GB5 sub tests isn’t being selective to fudge the geomean?

I told you, smart money is that both are fudging a bit. I'm not saying that AMD isn't fudging. But AMD obviously could have picked tasks that looked less suspicious and still ended up with a higher IPC if they wanted to. For whatever reason, they didn't.

HurleyBird · Jun 4, 2024

tamz_msc said:
SMT is irrelevant for ST, only relevant for MT in workloads like rendering which aren't done on the CPU anyways.

Of course it's irrelevant for ST. As far as only being relevant for tasks that are done on GPUs, lol.

tamz_msc · Jun 4, 2024

HurleyBird said:
Of course it's irrelevant for ST. As far as only being relevant for tasks that are done on GPUs, lol.

Ian's 3DPM is weird code - for every workload that scales like 3DPM does with SMT, I can find another scientific workload that scales in the opposite direction.

4-5 of those are renderers. Who uses the CPU for rendering?

That leaves us with 7-zip. The only relevant consumer workload that shows some benefit from SMT.

H433x0n · Jun 4, 2024

HurleyBird said:
I told you, smart money is that both are fudging a bit. I'm not saying that AMD isn't fudging. But AMD obviously could have picked tasks that looked less suspicious and still ended up with a higher IPC if they wanted to. For whatever reason, they didn't.

The Lion Cove IPC figure was pulled directly from Specint 1-copy, GB5, GB6, CB R23 & CB R24.

As far as I can tell AMD didn’t provide a Specint 1-copy number. They didn’t provide a GB5, GB6 or CB R24 number either.

Completely different method of calculating IPC. In comparison, it’s not even close to being as transparent.

majord · Jun 4, 2024

invisible_city said:
Because they’re not doing anything new and afraid to take risks. They’ve succumbed to incumbent inertia. Skymont laps them in mobile, and Zen 5 desktop parts are meh. Not pushing core counts, efficiency still way behind Apple/Qualcomm/ and now Intel, despite having access to TSMC. GPUs suck. And this is with a nearly dead Intel.

AMD will continue to dominate servers, but pace of innovations has slowed and that will come down too if something doesn’t change. Competition tends to motivate though.

while it may be the case , not making claims either way, but why are you so confident they're "lapped" in mobile by skymont?

tamz_msc said:
Intel's are less likely to be fudged because they are transparent on the OS, compiler, and benchmark used, while mentioning them in the slide, and not in the end-notes.

As for SMT or lack thereof, it's insignificant.

View attachment 100438

View attachment 100439

20% is insignificant?

tamz_msc · Jun 4, 2024

majord said:
while it may be the case , not making claims either way, but why are you so confident they're "lapped" in mobile by skymont?

20% is insignificant?

Don't look at the averages. Look at what's relevant.

DrMrLordX · Jun 4, 2024

tamz_msc said:
Ian's 3DPM is weird code

There is also 3DPM v2 which corrects the cache thrashing issue and has some other nice upgrades. It probably doesn't scale so well with SMT.

Also kudos to Intel for Skymont. It'll be interesting to see how Arrow Lake-S shapes up. The ST predictions for Arrow Lake-S may still come true, but I think +20% MT for Arrow Lake-S vs Raptor Lake-S @ PL2=253W is overly conservative.

Henry swagger · Jun 4, 2024

ondma said:
Seriously? This thread is getting way ahead of itself. I thought I saw leaks that Zen 5 will have similar clocks, and dont forget ARL is giving up hyperthreading, so the E cores better be really good. ARL will still have to have a really good IPC increase for the P cores to beat Zen 5.

Dnt worry 8+32 model should take care of zen 5 and zen6

coercitiv · Jun 4, 2024

Lunar Lake vs. Meteor - Lion Cove performance uplift over Redwood Cove drops to around 10% near the end of the power curve. Against Raptor Cove it would a bit lower still, not at the same power though. The main benefits are at lower clocks, where we get 18%+ performance, Raptor Cove would probably look silly here.

Looks to me like we're finally going to get a chip optimized for low power. I wonder how much of this is influenced by the TSMC node.

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