That is very interesting indeed. Why do split decoders? What's the benefit? Why not a monolithic 8-wide decoder?
That is very interesting indeed. Why do split decoders? What's the benefit? Why not a monolithic 8-wide decoder?Zen 5 was supposed to focus on efficiency as per FAD2022. Quite odd there was no mention of it.
Dual decode seems interesting, so Z5 would now be 8 wide (2x 4 wide), Tremont style.
They can gate off the second decoder block when not needed, for instance when there are no branch instructions/not multiple inst streams.That is very interesting indeed. Why do split decoders? What's the benefit? Why not a monolithic 8-wide decoder?
Dual decoders might benefit SMT. Since Intel is removing HT, it would give AMD a nice advantage in multi threaded workflows especially in mobile. With increased ALU count and bigger dispatch window, Z5 could see significat improvement in SMT performance relative to Z4.That is very interesting indeed. Why do split decoders? What's the benefit? Why not a monolithic 8-wide decoder?
Clustered decode such as in Tremont is an attempt to solve the x86 vs ARM argument, where the variable instruction decode makes it more complex to decode thus require more transistors(thus more area and power). The relationship is said to be roughly quadratic. So the impact gets worse and worse with more decoders.That is very interesting indeed. Why do split decoders? What's the benefit? Why not a monolithic 8-wide decoder?
It can, but not really.They can gate off the second decoder block when not needed, for instance when there are no branch instructions/not multiple inst streams.
However the inner details could be different and whether they can have same throughput as a single 8 wide is unlikely.
Maybe, but not the idea behind it.Dual decoders might benefit SMT. Since Intel is removing HT, it would give AMD a nice advantage in multi threaded workflows especially in mobile. With increased ALU count and bigger dispatch window, Z5 could see significat improvement in SMT performance relative to Z4.
IIRC what is quadratic is the number of possibilities of instruction lengths in a fetch packet. But there are ways to get around the issue by annotating data in the Icache lines. You pay the prices of variable length instructions once (until the line is evicted of course).Clustered decode such as in Tremont is an attempt to solve the x86 vs ARM argument, where the variable instruction decode makes it more complex to decode thus require more transistors(thus more area and power). The relationship is said to be roughly quadratic. So the impact gets worse and worse with more decoders.
By splitting the decoders into smaller portions, you get to reduce that impact. There is likely some performance impact there, but a well-executed team(like the Intel Austin one) will make balanced compromises.
I heard from an architect that the differences aren't just in the decoders, but yea what you said.IIRC what is quadratic is the number of possibilities of instruction lengths in a fetch packet. But there are ways to get around the issue by annotating data in the Icache lines. You pay the prices of variable length instructions once (until the line is evicted of course).
IIRC what is quadratic is the number of possibilities of instruction lengths in a fetch packet. But there are ways to get around the issue by annotating data in the Icache lines. You pay the prices of variable length instructions once (until the line is evicted of course).
Yes but it should be followed up in two forms:They could have made a lot better presentation on that keynote though.
There are only rumors (edit: and work-in-progress code submissions to gcc).Can someone joggle my memory, where have we info about exec. resources?
Are you implying that Zen 5 is wider than Zen 4? Careful now, because:Usually when AMD widened core, it came with substantial "ipc" improvements. This core baffles me.
So far, the only released info related to the core width are the gcc patches.
- No Leaks
- No speculation unrelated to publicly released technical materials/patches/manuals etc.
GCC patches are already final, and merged in GCC14, they are not work in progress.There are only rumors (edit: and work-in-progress code submissions to gcc).
Are you implying that Zen 5 is wider than Zen 4? Careful now, because:
So far, the only released info related to the core width are the gcc patches.
(This thread has been opened too early.)
Okay, that wasn't worded very well. I meant that this will have less influence because cache won't be shrinking much - and hence will become a larger and larger percentage of the die. Obviously, the shrinks will make a big difference difference in core logic. I just think that perf/watt (v/f curves for xtors) will be more dominant even is desktop design (being derivative anyway), as it appears to be from Zen5.Process node shrinks aren't going to be much of a help on the xtor/mm2 front going forward either. Going forward, node changes will be more towards power and performance improvements, IMHO.
That would indeed be good to have in post #1. There was more made public already besides what was said at Computex.More details will be added once they are public like die size, architecture details etc.
Launch in July --> July 31a rumored "Zen 5 Tech Day" in early July!
Why put this here? This is not official stuffsZen 5 抢先体验：Ryzen AI 9 365 (Strix Point SoC) 简单测试 | David Huang's Blog
Juicy technical stuff (most of which I'm not qualified to understand but the resulting discussion should be interesting!).
From the interview. Interesting.A Video Interview with Mike Clark, Chief Architect of Zen at AMD
Today’s “article” is a little bit different to what you readers are used to. This article is a transcript of our video interview I conducted with Mike Clark at AMD. This was my fi…chipsandcheese.com
From the interview. Interesting.
"George Cozma: You know, for a single thread of it, let’s say you’re running a workload that only uses one thread on a given core. Can a single thread take advantage of all of the front-end resources and can it take advantage of both decode clusters and the entirety of the dual ported OP cache?
Mike Clark: The answer is yes, and it’s a great question to ask because I explain SMT to a lot of people, they come in with the notion that we don’t [and] they aren’t able to use all these resources when we’re in single threaded mode, but our design philosophy is that barring a few, very rare microarchitectural exceptions, everything that matters is available in one thread mode. If we imagine we are removing [SMT] it’s not like we’d go shrink anything. There’s nothing to shrink. This is what we need for good, strong single threaded performance. And we’ve already built that."