Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

TESKATLIPOKA · Jun 9, 2024

mikk said:
From all the sources I have seen there is no HT on ARL-S. Every source says this and we got some from Intel too. It is very very unlikely. From what we know only some server variants might ship with HT enabled.

But then will Arrow be limited to only 8P+16E=>24 threads, when even the predecessor had 32?
Ok, Arrow should still be more performant, but even so It looks like a regression.

P.S. I hope there is no additional E cluster just for idle.

FlameTail · Jun 9, 2024

Lunar Lake can scale upto 30W TDP, but it's also supposed to be used in fanless laptops.

What's the maximum TDP a fanless laptop would support?

Khato · Jun 9, 2024

DrMrLordX said:
~10% die area is committed to HT? That's hard to believe. Also the extra power consumption only occurs when the HT core is forced to handle two threads, no?

All the structures required for HT don't disappear when HT isn't active. Even if they're clock gated to avoid all dynamic power they'll still use some amount of static power.

Regarding the 10% core die area to enable HT, keep in mind that also includes the many security structures which are only necessary for a HT enabled core.

Magio · Jun 9, 2024

FlameTail said:
Lunar Lake can scale upto 30W TDP, but it's also supposed to be used in fanless laptops.

What's the maximum TDP a fanless laptop would support?

Well, the best point of comparison would be an M3 Macbook Air. It seems to be able to sustain 10/11W of power with (very) short bursts at 20W. Notebookcheck.

The rumor from leaked slides was that Intel was targeting a 8W TDP PL1 for Lunar Lake's fanless mode which I could see be paired up with a 20W PL2. You could theoretically go higher on both counts by beefing up the passive cooling, but really you don't want a PL1 much higher than 10W if you're doing a fanless thin and light.

However considering they haven't said a word about fanless publicly so far I think it's fair to wonder if maybe that's no planned anymore. Could be they weren't able to reach their performance targets at 10-ish Watts of sustained power and scrapped it.

naukkis · Jun 9, 2024

DrMrLordX said:
~10% die area is committed to HT? That's hard to believe. Also the extra power consumption only occurs when the HT core is forced to handle two threads, no?

Ht enlarge structures in cpu critical paths. Removing it is much like going one node forward with manufacturing process. And yes, when cpu critical path is made larger power use stay high even when those parts for two threads aren't used. Maybe that can work around by design that has lower frequencies for SMT. Intel designs have lacked that kind of design philosophy.

lightisgood · Jun 9, 2024

DrMrLordX said:
Also the extra power consumption only occurs when the HT core is forced to handle two threads, no?

Based on LNL's design philosophy, if there is busy Lion Cove frequently, that is no less than a waste of power consumption.
Intel dosen't aim at squeezing LNC performance from the start.

mikk · Jun 9, 2024

FlameTail said:
Lunar Lake can scale upto 30W TDP, but it's also supposed to be used in fanless laptops.

What's the maximum TDP a fanless laptop would support?

It depends on the design and how big it is, I would say between 4-10W on a laptop. On LNL there is a 8W fanless option for Lunar Lake which is optional and this includes the on package RAM. Most designs should use 17W.

SiliconFly · Jun 9, 2024

Just saw F1 race demo on Lunar Lake running at 60fps in 1080p. That means, LNL Battlemage with XeSS is on par with RTX 3050 mobile. This is serious gaming muscle. Covers almost all casual gamers (only excluding pro gamers who require high end cpus & tons of graphics power).

This also means third party discreet gpus aren't needed in mid-range laptops anymore.

eek2121 · Jun 9, 2024

inf64 said:
It really seems that there is a chance ARL-S has HT enabled on its P cores, based on that video. Interesting decisions for P core in LNL.

Arrow Lake will have hyperthreading.

Triskain · Jun 9, 2024

Arrow Lake will have hyperthreading.

No, it won't.

eek2121 · Jun 9, 2024

Triskain said:
No, it won't.

The Intel rep that said it will said otherwise. I think he knows better than random internet guy #567,345,124.

Triskain · Jun 9, 2024

eek2121 said:
The Intel rep that said it will said otherwise. I think he knows better than random internet guy #567,345,124.

And what exactly did he say? Arrow Lake's Lion Cove will have more L2 Cache than Lunar Lakes's (3MB instead of 2.5), that just about covers the extent of the "differentiation" between them...

Hulk · Jun 9, 2024

DrMrLordX said:
~10% die area is committed to HT? That's hard to believe. Also the extra power consumption only occurs when the HT core is forced to handle two threads, no?

This is from the senior principal P core engineer and Intel slides.

HT adds 10% die area and additional power usage even when running ST.

inf64 · Jun 9, 2024

Triskain said:
And what exactly did he say? Arrow Lake's Lion Cove will have more L2 Cache than Lunar Lakes's (3MB instead of 2.5), that just about covers the extent of the "differentiation" between them...

To be honest, the language he used was very vague so we don't know if there are more differences between the two.

eek2121 · Jun 9, 2024

Triskain said:
And what exactly did he say? Arrow Lake's Lion Cove will have more L2 Cache than Lunar Lakes's (3MB instead of 2.5), that just about covers the extent of the "differentiation" between them...

if i get bored i will dig up a video for part of it: according to Intel, Lion Cove is an "architecture" (not a "Core", an "architecture") that has "many" configurable options, including hyper-threading, that can be turned on and off as needed. Hyperthreading was turned off for Lunar Lake to save area and power. They said all of this on video, I'm sure you can find it.

For the more direct answer, it is coming soon. It wasn't communicated to me in any way I can show proof so you'll have to wait (or talk to an Intel rep).

Everything I've seen indicates Intel has actually done something few (any?) companies ever have, and I don't think they are being given enough credit. Based on their claims, they have made a silicon design that is highly configurable and easily portable between nodes/processes of multiple vendors. That is, Intel can quickly spin up a chip with Lion Cove cores in it on either TSMC or Intel processes, and on either N3/N5 or Intel 4/3/20A/18A with minimal effort. They can do this while also turning on/off or configuring major features.

In lunar lake, for example, L2 cache was cut down and also L1->L2 bandwidth, hyper-threading removed, AVX--512 is "supposedly" not present, and more. Lion Cove server cores will have none of those limitations, and desktop will be optimized around whatever makes sense for Arrow Lake.

Henry swagger · Jun 9, 2024

https://twitter.com/x/status/1799525678032838797

Skymont 4.5ghz to 5ghz clocks ?🤔..

invisible_city · Jun 9, 2024

DrMrLordX said:
~10% die area is committed to HT? That's hard to believe. Also the extra power consumption only occurs when the HT core is forced to handle two threads, no?

Why is it hard to believe?

invisible_city · Jun 9, 2024

Triskain said:
No, it won't.

We don’t know it won’t. It does seem unlikely, because Intel in Hulk’s linked presentation highlights HT benefits in thread-dense servers, but theoretically possible due to Lion Cove’s modularity. At Computex, Intel also said they would add HT where the performance benefits existed and power wasn’t as much of a concern.

StinkyPinky · Jun 9, 2024

Does anyone know when we are actually getting some sku's? These things must be many months away if we don't even have that.

invisible_city · Jun 9, 2024

StinkyPinky said:
Does anyone know when we are actually getting some sku's? These things must be many months away if we don't even have that.

September at Intel On. We’ll see leaks before then.

SiliconFly · Jun 9, 2024

eek2121 said:
The Intel rep that said it will said otherwise. I think he knows better than random internet guy #567,345,124.

No Intel chip designers have explicitly stated that LNC in ARL will have HT. Some of the things they said kinda implies that ARL may get HT. Even I think it will. But Intel hasn't confirmed it yet.

And about HT, the P core designer said it in very high clarity the same thing I've been saying all along. HT kicks in and gives the performance increase only after all physical cores gets fully saturated during heavy multi-threaded workloads. And imho, this situation is not useful for most consumers and completely useless when there are plenty of E cores. HT is archaic and should just die.

Henry swagger said:
https://twitter.com/x/status/1799525678032838797
Skymont 4.5ghz to 5ghz clocks ?🤔..

4.6GHz is the best leak we've had till now.

StinkyPinky said:
Does anyone know when we are actually getting some sku's? These things must be many months away if we don't even have that.

In a month or two since they're targeting a sep launch.

Hitman928 · Jun 9, 2024

DrMrLordX said:
~10% die area is committed to HT? That's hard to believe. Also the extra power consumption only occurs when the HT core is forced to handle two threads, no?

It’s 10% core area, probably not including L2 which means it ends up being like 0.3% of the compute die area for each of the four P-cores in LNL.

invisible_city · Jun 9, 2024

eek2121 said:
if i get bored i will dig up a video for part of it: according to Intel, Lion Cove is an "architecture" (not a "Core", an "architecture") that has "many" configurable options, including hyper-threading, that can be turned on and off as needed. Hyperthreading was turned off for Lunar Lake to save area and power. They said all of this on video, I'm sure you can find it.

For the more direct answer, it is coming soon. It wasn't communicated to me in any way I can show proof so you'll have to wait (or talk to an Intel rep).

Everything I've seen indicates Intel has actually done something few (any?) companies ever have, and I don't think they are being given enough credit. Based on their claims, they have made a silicon design that is highly configurable and easily portable between nodes/processes of multiple vendors. That is, Intel can quickly spin up a chip with Lion Cove cores in it on either TSMC or Intel processes, and on either N3/N5 or Intel 4/3/20A/18A with minimal effort. They can do this while also turning on/off or configuring major features.

In lunar lake, for example, L2 cache was cut down and also L1->L2 bandwidth, hyper-threading removed, AVX--512 is "supposedly" not present, and more. Lion Cove server cores will have none of those limitations, and desktop will be optimized around whatever makes sense for Arrow Lake.

Right, I think the encouraging thing is that if HT is not included on Arrow Lake it is likely because not including HT was the better option for whatever power envelope Intel was targeting, rather than because they took a guess at the implications early in development and by the point the discovered HT was net benefit, it was too late.

Or even worse, that they tried to make HT work and couldn't.

invisible_city · Jun 9, 2024

SiliconFly said:
No Intel chip designers have explicitly stated that LNC in ARL will have HT. Some of the things they said kinda implies that ARL may get HT. Even I think it will. But Intel hasn't confirmed it yet.

And about HT, the P core designer said it in very high clarity the same thing I've been saying all along. HT kicks in and gives the performance increase only after all physical cores gets fully saturated during heavy multi-threaded workloads. And imho, this situation is not useful for most consumers and completely useless when there are plenty of E cores. HT is archaic and should just die.

4.6GHz is the best leak we've had till now.

In a month or two since they're targeting a sep launch.

Right, my 32 thread 5950x has 16 good threads, and 16 redacted ones that perform at best like 1/3rd the speed of the 16. This means that when making HPC apps, I have to be careful to design around that fact, or expect that things close to 16 cores not 32. Made worse by the fact that in some cases having HT enabled makes the 16 "good" threads individually slower. HT sucks and was a bandaid in the era when 32 cores on a die were unthinkable, never mind 144. We're past that, so HT needs to go away and Intel needs to drive core counts up by spamming Skymont.

I want to see a 64 core consumer part, with 8 lion cove for low-thread scenarios.

edit: Also, if Intel does ever get rentable units working, Chadmont will reach its final form, GigaChad.

No profanity in tech.

esquared
Anandtech Forum Director

dttprofessor · Jun 9, 2024

Henry swagger said:
https://twitter.com/x/status/1799525678032838797
Skymont 4.5ghz to 5ghz clocks ?🤔..

It's incredible，5G?

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Senior member

Attachments

Platinum Member

Diamond Member

Golden Member

Junior Member

Senior member

Senior member

Attachments

Diamond Member

Golden Member

Diamond Member

Member

Diamond Member

Member

Diamond Member

Diamond Member

Diamond Member

Senior member

Member

Member

Diamond Member

Member

Golden Member

Diamond Member

Member

Member

Member