Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

DrMrLordX · Jun 10, 2024

edit: somehow a quote wandered over from the Zen5 thread and I'm not sure how it got here. Either that or I was in an off-topic conversation so I've deleted my response.

Ghostsonplanets said:
6+8 is both TSMC and Intel.

Huh, how will Intel handle sourcing the 6+8 tile from different foundry companies? Are they going to mix and match within the same SKU or parcel them out to different SKUs based on the source foundry?

Elfear · Jun 10, 2024

SiliconFly said:
Best case they might even add another 15% IPC. LNC in ARL isn't just an updated LNC in LNL. They were working in parallel from the beginning. Those two might be entirely different beasts for all we know.

Also remember, LNC in LNL isn't allowed to stretch it's legs due to power/thermal constraints. Not so in case of ARL. Some free bonus there too.

We may just receive 2% to 3% IPC uplift (over LNC in LNL) like you said. Or we may end up with a massive 30% uplift. Who knows? We can only speculate until they say so.

Has a 15-30% IPC increase ever happened on the same basic core design? Genuinely asking here. That would be like the same IPC increase we saw from RWC --> LNC on the low-end or Cypress Cove to LNC on the high-end. That seems so far outside the realm of possible...

SiliconFly · Jun 10, 2024

Elfear said:
Has a 15-30% IPC increase ever happened on the same basic core design? Genuinely asking here. That would be like the same IPC increase we saw from RWC --> LNC on the low-end or Cypress Cove to LNC on the high-end. That seems so far outside the realm of possible...

Interesting. Someone just forgot about the recent Crestmont to Skymont.

Things happen. Both with AMD & Intel. We can never be sure of what to expect in this climate.

Ghostsonplanets · Jun 10, 2024

DrMrLordX said:
Huh, how will Intel handle sourcing the 6+8 tile from different foundry companies? Are they going to mix and match within the same SKU or parcel them out to different SKUs based on the source foundry?

From what I know, N3B 6+8 should be the highest volume at first, with 20A being lower volume. 20A ramp up later, with (maybe), getting the lions share of 6+8 die volume.

And 6+8 20A die is exclusively Desktop. Mobile is only 6+8 TSMC N3B.

DrMrLordX · Jun 10, 2024

Ghostsonplanets said:
And 6+8 20A die is exclusively Desktop. Mobile is only 6+8 TSMC N3B.

Okay, that answers my question: they won't mix & match within the same SKU. Which makes sense.

H433x0n · Jun 10, 2024

Elfear said:
Has a 15-30% IPC increase ever happened on the same basic core design? Genuinely asking here. That would be like the same IPC increase we saw from RWC --> LNC on the low-end or Cypress Cove to LNC on the high-end. That seems so far outside the realm of possible...

The odds of that are like 0.01%. Realistically a 2-5% above Lunar Lake’s variant of Lion cove is best case scenario for ARL-S.

The only way I can see it exceeding that is if they somehow reduce latency significantly with the SoC tile designed for desktop.

Edit: Why am I being downvoted / reported for a benign statement?

Thunder 57 · Jun 10, 2024

H433x0n said:
The odds of that are like 0.01%. Realistically a 2-5% above Lunar Lake’s variant of Lion cove is best case scenario for ARL-S.

The only way I can see it exceeding that is if they somehow reduce latency significantly with the SoC tile designed for desktop.

Edit: Why am I being downvoted / reported for a benign statement?

People gonna hate. Have yourself an upvote.

invisible_city · Jun 10, 2024

H433x0n said:
The odds of that are like 0.01%. Realistically a 2-5% above Lunar Lake’s variant of Lion cove is best case scenario for ARL-S.

The only way I can see it exceeding that is if they somehow reduce latency significantly with the SoC tile designed for desktop.

Edit: Why am I being downvoted / reported for a benign statement?

I agree, expecting 2x performance gain by moving from low power design to high power design seems wildly optimistic. If they include HT, I could see MT gaining that extra 20%, but IPC for single threaded workloads isn't changing by an additional 15%.

Hulk · Jun 10, 2024

Elfear said:
Has a 15-30% IPC increase ever happened on the same basic core design? Genuinely asking here. That would be like the same IPC increase we saw from RWC --> LNC on the low-end or Cypress Cove to LNC on the high-end. That seems so far outside the realm of possible...

No. We used to call that a "tick." 5% is all we ever saw and it was usually due to very minor core/cache/memory subsystem changes.

Golden Cove to Raptor Cove would have been a tick back in the tock-tock days. Large L2 cache, more cores, and a process stepping.

Hulk · Jun 10, 2024

DrMrLordX said:
Okay, that answers my question: they won't mix & match within the same SKU. Which makes sense.

Could you imagine the mess that would cause? Kind of like SSD manufacturers using different NAND vendors. "Hey, did you get the Intel 20A or the TMSC N3B CPU tile on your ARL? I hear the memory controller is generally better on the Intel node but the TMSC clocks higher with less voltage. I'm gonna return mine and try again."

Joe NYC · Jun 11, 2024

SiliconFly said:
Interesting. Someone just forgot about the recent Crestmont to Skymont.

Things happen. Both with AMD & Intel. We can never be sure of what to expect in this climate.

It is much easier to increase IPC when starting from low IPC base (previous gen E-Cores) than from a much higher base (previous gen P-Cores)

Especially when given extra transistors, extra die area, extra power budget.

FlameTail · Jun 11, 2024

What would be the performance ratio of Lunar Lake's 'P-core : E-core'? Curious to know.

For comparison, Apple M3's ratio is 3 : 1.

coercitiv · Jun 11, 2024

FlameTail said:
What would be the performance ratio of Lunar Lake's 'P-core : E-core'? Curious to know.

For comparison, Apple M3's ratio is 3 : 1.

According to Intel it's 3:2

DrMrLordX · Jun 11, 2024

Hulk said:
Could you imagine the mess that would cause? Kind of like SSD manufacturers using different NAND vendors. "Hey, did you get the Intel 20A or the TMSC N3B CPU tile on your ARL? I hear the memory controller is generally better on the Intel node but the TMSC clocks higher with less voltage. I'm gonna return mine and try again."

Apple did it years ago with modems. They didn't just use different processes, they used entirely different OEMs (Intel and Qualcomm). That was quite a fiasco.

FlameTail · Jun 11, 2024

LNL has 3 display pipes. One would be used for internal display of laptop, meaning two remain for the external display.

So Lunar Lake laptops can only drive 2 external displays?

SiliconFly · Jun 11, 2024

FlameTail said:
View attachment 100949
LNL has 3 display pipes. One would be used for internal display of laptop, meaning two remain for the external display.

So Lunar Lake laptops can only drive 2 external displays?

3 displays (2+1) is more than sufficient. Even Apple doesn't support like 8 displays or anything like that. Not needed.

DavidC1 · Jun 11, 2024

SiliconFly said:
Interesting. Someone just forgot about the recent Crestmont to Skymont.

Things happen. Both with AMD & Intel. We can never be sure of what to expect in this climate.

But Skymont is a huge change, while you are talking about 15% gains in essentially a near identical architecture.

The expectations are insane, such as 40% for Zen 5. Arrowlake uses the same tile configuration as Meteorlake, and Lunarlake is using a much saner approach. If anything, Lunarlake's Lion Cove should be faster than Lion Cove in Arrowlake.

I'd say your conclusions are insane, but I won't because I know you still got lot to learn.

Joe NYC said:
It is much easier to increase IPC when starting from low IPC base (previous gen E-Cores) than from a much higher base (previous gen P-Cores)

Sure, but Apple has got it MUCH higher and even the ARM teams. This means the E core team is on the right track(still got ways to go) while the P core team needs a drastic overhaul, maybe a complete abandonment of the basic design.

14% difference per clock with near 3x difference should be a clue for everybody.

If they continue on the same path, Novalake will be a chip where P core's only advantage is in clocks, while still having the massive 3:1 area disadvantage. If the problem is due to the P core management and members being arrogant, the only way is to embarass them to destroy their attitude. Maybe bring the difference in core size down to 2:1 and beat the P core by 15% per clock.

Imagine if Conroe was a chip where it had Netburst and Core cores in one silicon.

FlameTail · Jun 11, 2024

SiliconFly said:
3 displays (2+1) is more than sufficient. Even Apple doesn't support like 8 displays or anything like that. Not needed.

3 vs 8 is huge number. I think there is a sizable number of people who use 3-4 external displays. Not sure.

SiliconFly · Jun 11, 2024

DavidC1 said:
...essentially a near identical architecture. ...

That is the point of contention. I'm saying there is a good chance that ARL's LNC can have more significant changed over LNL's LNC. And as of now, only Intel know the facts. We can only assume either one way or the other...

SiliconFly · Jun 11, 2024

FlameTail said:
3 vs 8 is huge number. I think there is a sizable number of people who use 3-4 external displays. Not sure.

I've seen some using 3. But those are for gaming. And sadly, LNL isn't for pro-gamers.

CouncilorIrissa · Jun 11, 2024

I'd wager there’s a very small intersection between people who benefit from LNL's performance on the go AND those doing the type of work that requires 4 or more monitors. If you have so many monitors it’s very likely that you have an actual workstation next to them.

coercitiv · Jun 11, 2024

CouncilorIrissa said:
I'd wager there’s a very small intersection between people who benefit from LNL's performance on the go AND those doing the type of work that requires 4 or more monitors.

I bet I could fit these people on 2 monitors.

Hulk · Jun 11, 2024

FlameTail said:
View attachment 100949
LNL has 3 display pipes. One would be used for internal display of laptop, meaning two remain for the external display.

So Lunar Lake laptops can only drive 2 external displays?

It can drive 3 external when the lid is closed.

invisible_city · Jun 11, 2024

Hulk said:
It can drive 3 external when the lid is closed.

I have to say, I prefer one medium-size TV as a monitor to many small ones. Mostly for the after work entertainment, but at some point too much stuff on screen is distracting.

Wolverine2349 · Jun 11, 2024

Is Arrow Lake going to inherit exact same core to core latency as Meteor Lake or could it be improved?

How would you say Meteor Lake core to core latency is compared to 13th and 14th Gen and also AMD core to core latency within a CCX?

It seems AMD core to core latency is great within a CCX but once it leaves a CCX/CCD< it is a massive 3 to 4 times increase hit.

Intel seems more consistent though still a 10-20% increase going to the e-cores rather than 300-400% increase AMD has crossing CCX/CCD/

Though could Arrow Lake make core to core latency relatively equal between P and e-cores where as 12th to 14th Gen has like a 15-20% increase going form P to e-core.

I noticed slides for Meteor Lake seemed to suggest yes, but at same time some core to core latency form P core threads seemed a little more inconsistent as in 15-20% hit in MTL than 13th and 14th Gen. Though not sure if they can fix that and maybe that was poor hyper threading latency implementation crossing threads on P cores of Meteor Lake?

And if latency is consistent and good between all cores P and E within a single tile on Arrow Lake would it likely be the better choice than AMD Ryzen 9000 for CPU thread heavy games??

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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