Of course designs are simulated, about 100% accuracy nowadays.
My day job is to write these kinds of simulators. "Tweaking" them to study micro architecture ideas is extremely costly. As costly if not more than writing the RTL after the directions are known because you have to test several ideas. And once you're done with that, you can't run large workloads because simulation is slow.
And I have horrible news for you: these simulators never are 100% accurate, quite close, but untested areas are bound to be inaccurate and propagate inaccuracies all over the place.
So no, simulation is not the miracle solution in particular when playing with features that have system wide impact such as SMT. You can write a prototype but as long as you don't spend time tuning it and discussing with RTL engineers you don't know if it makes sense or not and if the projected performance is meaningful in any way. Yes, that's extremely costly.
Of course that doesn't apply when you play with toy uarch as found in low-end CPU where basically nothing happensy. But that's not what we're discussing here.
And then power simulation often is very inaccurate (10% or more is common) and runs so slowly that you can't run long sequences of code. One can extrapolate statistical results but that's it. That gives rough ideas.
I'm not saying Intel didn't do that. I say it's so costly that it wouldn't make sense to make a very thorough pertinent analysis.