Discussion Apple Silicon SoC thread

Eug · Nov 10, 2020

M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:

M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

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M1 Ultra discussion here:

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M2 discussion here:

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Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

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M4 Family discussion here:

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igor_kavinski · Jun 17, 2024

poke01 said:
And how is this any different than ARM or Qualcomm? They also push clocks.

Those two have nowhere near the amount of cash that Apple is sitting on.

One would think that they would come up with something original, other than pushing clocks.

Unless, their best and brightest are too busy working on the next big thing. Which is fine I guess. But I'm calling it right now. If M5 is more of the same thing, they've hit a wall.

And then they will have to design their own ISA. The Apple Quantum ISA. Where 2+2 may be any value from 0 to 4, because there is the added uncertainty of apples being rotten or having worms in them.

SarahKerrigan · Jun 17, 2024

igor_kavinski said:
Those two have nowhere near the amount of cash that Apple is sitting on.

One would think that they would come up with something original, other than pushing clocks.

Unless, their best and brightest are too busy working on the next big thing. Which is fine I guess. But I'm calling it right now. If M5 is more of the same thing, they've hit a wall.

Microsarchitecture is hard and there's a limited talent pool.

That's not to say they haven't hit a wall in terms of large inter-generational improvements, but like, there is no service for turning money into an aggressive microarchitecture cadence - nor are semiconductor teams and projects quick to ramp up.

igor_kavinski · Jun 17, 2024

SarahKerrigan said:
but like, there is no service for turning money into an aggressive microarchitecture cadence - nor are semiconductor teams and projects quick to ramp up.

They have money to burn on moonshot ideas and they can actually afford to do a few of them in parallel. But their priority is battery life and thin form factor. At this rate, we may end up with an Apple device that people plug into their butts (with obviously a disposable safety plug) that then uses the nerve endings in that region to communicate with the brain and offload all processing to it. Battery running out? Drink lemonade! More processing power you say? Drink coffee!

poke01 · Jun 17, 2024

igor_kavinski said:
Those two have nowhere near the amount of cash that Apple is sitting on.

One would think that they would come up with something original, other than pushing clocks.

Unless, their best and brightest are too busy working on the next big thing. Which is fine I guess. But I'm calling it right now. If M5 is more of the same thing, they've hit a wall.

And then they will have to design their own ISA. The Apple Quantum ISA. Where 2+2 may be any value from 0 to 4, because there is the added uncertainty of apples being rotten or having worms in them.

Qualcomm does have more talent than Apple now in CPU department.

You would think that dedicated chip companies will be far ahead of Apple but it doesn’t look limit it. Qualcomm will push clocks this year and next year as well a improving the architecture a bit.

I really don’t get why you have this fetish of Apple abandoning arm64 ISA anytime soon when they signed a deal with ARM for 40 years. RISC-V is also too immature now and is not needed for Apple.

poke01 · Jun 17, 2024

igor_kavinski said:
They have money to burn on moonshot ideas and they can actually afford to do a few of them in parallel. But their priority is battery life and thin form factor. At this rate, we may end up with an Apple device that people plug into their butts (with obviously a disposable safety plug) that then uses the nerve endings in that region to communicate with the brain and offload all processing to it. Battery running out? Drink lemonade! More processing power you say? Drink coffee!

Money means nothing without proper management and also talent. Microsoft couldn’t even make a phone or phone ecosystem to work. Intel can’t make powerful GPUs, Nvidia can’t make custom CPU’s and Apple couldn’t make a car.

I’m not going to address the other half the post cause you have some weird thoughts.

The Hardcard · Jun 17, 2024

igor_kavinski said:
Those two have nowhere near the amount of cash that Apple is sitting on.

One would think that they would come up with something original, other than pushing clocks.

Unless, their best and brightest are too busy working on the next big thing. Which is fine I guess. But I'm calling it right now. If M5 is more of the same thing, they've hit a wall.

And then they will have to design their own ISA. The Apple Quantum ISA. Where 2+2 may be any value from 0 to 4, because there is the added uncertainty of apples being rotten or having worms in them.

Clocks in and the of themselves not a problem. The only problem would be if they have to go higher than their targets for power and energy consumption. Have they?

Were the M1 and M2 representative of Apple’s targets or did the designs run out of steam below what they wanted? Is the M4 the result of just busting the power budget, or is them finally reaching their original targets?

Anecdotal reports suggest the new iPad Pros maintain battery life with normal use. No one has shown any evidence yet that the IPC of the M4 was the result of Apple engineers having that goal and failing to reach it.

On top of which they are second to none and appear to be able to take that into 2025.

poke01 · Jun 17, 2024

https://twitter.com/x/status/1802764280078737836

more details about M4

name99 · Jun 17, 2024

Doug S said:
Up until the M4 iPad I think their cooling system was "eh, these CPUs sip power, it'll all work itself out"

Not completely true.
They have certainly thought about these issues, though perhaps have not yet had a reason to do anything specific: eg

https://patents.google.com/patent/US10714425B2

name99 · Jun 17, 2024

The Hardcard said:
Clocks in and the of themselves not a problem. The only problem would be if they have to go higher than their targets for power and energy consumption. Have they?

Were the M1 and M2 representative of Apple’s targets or did the designs run out of steam below what they wanted? Is the M4 the result of just busting the power budget, or is them finally reaching their original targets?

Anecdotal reports suggest the new iPad Pros maintain battery life with normal use. No one has shown any evidence yet that the IPC of the M4 was the result of Apple engineers having that goal and failing to reach it.

On top of which they are second to none and appear to be able to take that into 2025.

What we are seeing here is two things
- on the APPLE side, design changes when process changes. More companies should be that flexible...
I described Apple's path up to the M1, and that was an optimal path given the realities of the time (cheap transistors, cheap wiring). But elements of that path were clearly coming to an end as M1 shipped – wiring is becoming relatively more expensive, which means SRAM is more expensive, which means that for M2..M4 many M1 elements (anything that relied on speculation based on memory, ie local SRAM) had gone about as far as they could go.
But, in turn, other elements became available – in such an environment it made sense to reconsider how LOGIC (rather than SRAM) could be exploited, to boost frequency (as long as that didn't result in a power explosion, and especially, did not hurt idle power), along with boosting logic-related elements, like width.

Presumably backside metal changes the equation again. There will be a brief period where backside metal allows for denser SRAM, meaning probably that for that brief period adding more branch prediction and prefetch SRAM (and other options, maybe value prediction?) make sense.
But then backside metal will be mined out.
After that we will get 3D chips. This probably allows the movement of large SRAMs (L2 and bigger) off the "main" level, so what's the optimal way to use the area that is freed? Making AMX/SME much larger? Adding special bypasses so that CPU<->GPU<->ANE communication can be much lower latency?

- on the INTERNET side, the bulk of the population is oblivious to any of this. For them, the way CPUs were designed when they learned about them is the one true way.
Most of the Intel guys are still living in a world where frequency and SMT are good ideas.
Most of the Apple guys still think it's some sort of betrayal that Apple devoted the M2..M4 to frequency rather than aggressive IPC scaling. (Even Geekerwan, bless his soul, doesn't seem to really appreciate that Apple's end goal is not high IPC, it's appropriate balancing of power and performance; and the best techniques for that on N7 are somewhat different from the best techniques on N3, which will in turn be different from the best techniques on TSMC A16.)

There is plenty of material still left to boost the speed of Apple's cores (or the cores of anyone else willing to put in the work). But the specific order in which those ideas get implemented is harder to predict, dependent as it is on details we can at least see (BSPD, GAA, in a few years 3D design), and elements that we can not (abilities of Apple's simulation and design software, particular interests of people on the design team, legal issues).

FlameTail · Jun 17, 2024

poke01 said:
more details about M4

Is the diet area given?

TwistedAndy · Jun 18, 2024

poke01 said:
I’m sure they will increase clocks but it’s probably the same as M3 clocks. And how is this any different than ARM or Qualcomm? They also push clocks.

Qualcomm is using lower clocks (3.3 - 3.4 GHz for SD 8 gen 3) and is making more architectural changes to their CPUs.

SarahKerrigan said:
Microsarchitecture is hard and there's a limited talent pool.

Especially when all the talents are sitting on this forum

The Hardcard said:
Clocks in and the of themselves not a problem. The only problem would be if they have to go higher than their targets for power and energy consumption. Have they?

It looks like Apple is targeting Intel Raptor Lake:

poke01 · Jun 18, 2024

TwistedAndy said:
Qualcomm is using lower clocks (3.3 - 3.4 GHz for SD 8 gen 3) and is making more architectural changes to their CPUs.

I meant for their upcoming chips

FlameTail · Jun 18, 2024

Apple M4 is nearly 170 mm². I did a rough measurement and calculation.

Can someone confirm?

The Hardcard · Jun 18, 2024

TwistedAndy said:
It looks like Apple is targeting Intel Raptor Lake:

View attachment 101369

The comment alone is funny, but posting a screenshot making sure to not use the one that includes Raptor Lake is hilarious. Comedy gold.

FlameTail · Jun 18, 2024

FlameTail said:
Apple M4 is nearly 170 mm². I did a rough measurement and calculation.
View attachment 101376
Can someone confirm?

@Hulk Can you labelling the die areas of invidual components for this M4 die shot, like you did with LNL?

FlameTail · Jun 18, 2024

Btw, it looks like M4 has an 8-core Neural Engine?

igor_kavinski · Jun 18, 2024

FlameTail said:
View attachment 101376

Woah. That's a very interesting design.

The SLC seems to be positioned to benefit the GPU.

The memory subsystem is catering to the GPU first, CPU clusters second.

Is one P-core cluster sharing the L2 with the NPU cluster?

It's a weird arrangement, especially with respect to the caches. Shouldn't the shared caches be in the middle of the clusters to be able to serve each core with the same latency?

What is all that unused space??? Dark silicon???

FlameTail · Jun 18, 2024

Here's M3 die shot for context:

TwistedAndy · Jun 18, 2024

The Hardcard said:
The comment alone is funny, but posting a screenshot making sure to not use the one that includes Raptor Lake is hilarious. Comedy gold.

There was a research regarding the Intel Core i7 13700K. One Raptor Cove P-core consumes 6.6W on 3.4 GHz. That's right in between M3 and M4.

If we increase the clock speed to 4.5 GHz, the P-core in Intel, running on the old 10nm node, consumes nearly the same amount of power (9W) as M4, working on the same 4.5 GHz and using a much finer node (3nm).

Can we consider that the Apple M4 power consumption target has been achieved?

igor_kavinski · Jun 18, 2024

FlameTail said:
Here's M3 die shot for context:
View attachment 101379

Looks similar to M4 except the P-core clusters have just one large slice of shared cache whereas M4's P-cores have smaller, independent slices. Maybe split off coz the smaller caches have lower latency? But then they introduced coherency overhead between the two separate P-core L2 caches. I wonder how much they gained after deducting the overhead?

The Hardcard · Jun 18, 2024

TwistedAndy said:
There was a research regarding the Intel Core i7 13700K. One Raptor Cove P-core consumes 6.6W on 3.4 GHz. That's right in between M3 and M4.

If we increase the clock speed to 4.5 GHz, the P-core in Intel, running on the old 10nm node, consumes nearly the same amount of power (9W) as M4, working on the same 4.5 GHz and using a much finer node (3nm).

Can we consider that the Apple M4 power consumption target has been achieved?

Now I get it. You are putting together a whole comedy act. Keep them coming 🤣

The M3 core matches the 14900K in SPEC when the Raptor Lake core is sucking down upwards of 30 watts, the M4 straight smokes it at 7.2 watts on integer and 8.95 watts on floating point. Then you point out that if one crushes that already defeated performance down so that the M4 laps it, you can have similar power draw. I guess that is a point. Why make it is my question.

Yes, I think it is possible that flawless victory with 10 watts could have been the original goal. Or maybe they want to go even higher. Maybe a 15 watt peak core was the original plan, given that 10 watts peak still allows all day use with a 31.3 Whr battery in a passively cooled 1 pound/.45 kilo device.

okoroezenwa · Jun 18, 2024

Yay, TwistedAndy found the ASi thread

Nothingness · Jun 18, 2024

I've decided to ignore him. I can't stand people who don't want to learn. He doesn't even know how register renaming works and wants to lecture everyone. The kind of guy who never admits he was wrong, as if being wrong was a problem... unless one insists on being wrong even when presented with evidence. And as he is polluting every thread I read, that was too much for me. It seems I'm not the only one to feel the pain.

Oh well, life goes on

TwistedAndy · Jun 18, 2024

The Hardcard said:
The M3 core matches the 14900K in SPEC when the Raptor Lake core is sucking down upwards of 30 watts, the M4 straight smokes it at 7.2 watts on integer and 8.95 watts on floating point. Then you point out that if one crushes that already defeated performance down so that the M4 laps it, you can have similar power draw. I guess that is a point. Why make it is my question.

Intel has no other option than to increase the clocks above any reasonable limits because they were stuck on the old 10nm node and 3-year-old Golden Cove cores.

Apple is also following this route. 100W under MT load is what we all want to see in M4 Max

FlameTail · Jun 18, 2024

Is nobody going to talk about 170 mm² die area for M4?

This is significant.

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