Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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Geddagod

Golden Member
Dec 28, 2021
1,202
1,166
106
The link's broken for me.
Oh that's my bad, I think I just failed copy pasting....
Here
I'll do you one better tho, here's one of the video that was referenced on:
28:40
It is either 16% now or 20%+ in 8 months, at some point time to market has more importance than a few % more IPC.
What? Sorry I'm very sleep deprived lol
No Geddagod, it was not a wish(can't say why).
What?
Successfully memed Zen5% into existence.
🤣

I mean across the board. It is not uncommon for a new architecture to show some little regression on some tests while being noticeably faster in the average. And If I understood correctly, he measured an average of slightly less than the advertised +16% iso clock in his set of application. So calling a +13-15% a "step back" is a kind of stretch, maybe disappointing if we think about the increase in the core area and time to market. It will depend on how many low hanging fruits there are, and if Zen6 will take advantage of those when using a denser process.
Oh no I was talking specific structure sizes. Apparently some stuff in the core for Zen 5 is significantly scaled back? (Presumably in the execution engine or some structures past the rename stage?) I'm assuming they expected the new massive front end to compensate. Who knows.
 

leoneazzurro

Golden Member
Jul 26, 2016
1,005
1,597
136
Oh no I was talking specific structure sizes. Apparently some stuff in the core for Zen 5 is significantly scaled back? (Presumably in the execution engine or some structures past the rename stage?) I'm assuming they expected the new massive front end to compensate. Who knows.
This seems very vague, probably when creating the front end not all the components have been duplicated, so in general there is an increase of the total resources available but less than it would have been expected in a comparison with Zen4.
 

Abwx

Lifer
Apr 2, 2011
11,166
3,860
136
What? Sorry I'm very sleep deprived lol

Zen+ had 5% better IPC than Zen, it wasnt due to any improvement but to the fact that to get Zen 1 to market earlier they had to reduce IPC for the chip to be perfectly stable
in its 14nm form, only with 12nm they could reduce internal latencies and get the actually projected IPC.

Same here, it s better to release a new CPU at 16% better IPC now than next year at 20%, financiarly it makes much more sense.
 

CouncilorIrissa

Senior member
Jul 28, 2023
295
1,034
96
Oh that's my bad, I think I just failed copy pasting....
Here
I'll do you one better tho, here's one of the video that was referenced on:
28:40
What he's saying makes a lot of sense (who would've thought that about Jim Keller of all people).

I guess we'll only see the full impact of Zen 5 uarch changes only in the future generations.
 

LightningZ71

Golden Member
Mar 10, 2017
1,658
1,940
136
That kind of maps to what I suspect; Zen5 was supposed to be a bit more, but when TSMC noted a delay in the N3 family of nodes, they had to use a contingency plan that dropped transistor count because they had maximum limits on die size that they couldn't go over. With the previously speculated idea that Zen6 wasn't going to be as big of a jump, what we may wind up seeing is that Zen6 winds up being more of a jump than originally planned, but still nothing drastic. With the rumored reductions in Strix Zen5 core capabilities as compared to desktop Zen5, and given how much was crammed into roughly the same package as Hawk Point ( 12 cores instead of 8, 2 more WGPs, cache for a second CCX, etc) it's understandable why these choices were made. N3 offered notable density improvements for the logic, which would have greatly impacted both the cores and the WGPs. Thus, you get RDNA 3.5 instead of RDNA4 and a cut down Zen5 instead of the full deal.

I'm not upset about it, just curious as to what it finally looks like in production on benchmarks.
 
Reactions: lightmanek

DisEnchantment

Golden Member
Mar 3, 2017
1,684
6,227
136
I remember watching interview with either Keller or Mike Clark few years back, in which one of them stated that new architecture does not mean major jump in performance, it means reworking things to not regress too much, but open new possibilities and options of improving no longer possible on older, fully developed architecture.
Already back then it was indicated that normal IPC jump is what they aim for in general.
If I find that quote I will link it here.


Mike also made this presentation, which stresses on multiple aspects of performance beyond IPC.

I guess we'll only see the full impact of Zen 5 uarch changes only in the future generations.
Z6 probably design complete by now, should be in implementation.
But it is going to get a clock bump moving to the new process N3E/N3P, so it is not going to look as bad as Z5.
 

yuri69

Senior member
Jul 16, 2013
435
717
136
Leaked slides already showed different FP width variants, why not?
View attachment 101542
There is a neat Zen 5 table by instlatx64:
That's 10 years like dead.
Doesn't look like that. Long development times with so so results.
Same here, it s better to release a new CPU at 16% better IPC now than next year at 20%, financiarly it makes much more sense.
People say:
* AMD nowadays got a lot of money from EPYC sales & gamerz buying X3D like 100x compared to Intel
* Intel not being a threat with the poor broken Lion Cove
* ARM is laughable

Besides, Zen 5 got a scope cut since it still reuses that Zen 2 IF architecture...

What's the rush then?

DisEnchantment said:
Z6 probably design complete by now, should be in implementation.
But it is going to get a clock bump moving to the new process N3E/N3P, so it is not going to look as bad as Z5.
Well, it doesn't look that good since the MLID's roadmap slide painted Zen 6 as a very light Zen 5 optimization with that 10% IPC figure. Note this figure is lower than Zen 4.
 

lightmanek

Senior member
Feb 19, 2017
399
798
136
Oh that's my bad, I think I just failed copy pasting....
Here
I'll do you one better tho, here's one of the video that was referenced on:

28:40

...

Thank you, this is exactly what I had in mind.

I'm very intrigued about Zen5 in both mobile and desktp/server form. Somehow I get a feeling they will differ a lot more than we are typically used to for each past generation, which I think is a good thing.
I want laptop to be fast, but also cool'n'quiet (pun intended), while desktop has to be efficient (where efficient doesn't mean low power, but a lot of work per joule of energy, like currently Zen4X3D or Apple's Mx processors).
 

Abwx

Lifer
Apr 2, 2011
11,166
3,860
136
People say:
* AMD nowadays got a lot of money from EPYC sales & gamerz buying X3D like 100x compared to Intel
* Intel not being a threat with the poor broken Lion Cove
* ARM is laughable

Besides, Zen 5 got a scope cut since it still reuses that Zen 2 IF architecture...

What's the rush then?


Well, it doesn't look that good since the MLID's roadmap slide painted Zen 6 as a very light Zen 5 optimization with that 10% IPC figure. Note this figure is lower than Zen 4.
They are selling their A0 silicon, wich say that they were pressed to release the chip as soon as possible, as for up to 6 months with no competition they can make a lot of money out of DT Zen 5.

Beside they are suley more concentrated in their mobile offerings, that s where there s actual competition and bigger volumes, so better to get rid of the DT parts and concentrate on the few mobile chips that are still under developpement like KRK and Strix Halo.
 

Goop_reformed

Senior member
Sep 23, 2023
246
301
96
They are selling their A0 silicon, wich say that they were pressed to release the chip as soon as possible, as for up to 6 months with no competition they can make a lot of money out of DT Zen 5.

Beside they are suley more concentrated in their mobile offerings, that s where there s actual competition and bigger volumes, so better to get rid of the DT parts and concentrate on the few mobile chips that are still under developpement like KRK and Strix Halo.
Zen 5 did indeed have problems. Notice the 2 months gap between release date and announcement.
 

Hitman928

Diamond Member
Apr 15, 2012
5,593
8,764
136
If STX is not actually 512b wide FP then why did they double the cache bandwidth and why is the core so much bigger?

If STX is scoring 3000 pts in GB6 at 5 GHz, that puts it right about 20% higher PPC in GB6. We previously had a range of ~17% - 25% PPC from previous leaks so this fits in with those prior scores.
 
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