I think GR and Strix will do just fine against ARL. It's just us geeks having too high of expectations form AMD, they spoiled us with previous Zen iterations.If STX is not actually 512b wide FP then why did they double the cache bandwidth and why is the core so much bigger?
If STX is scoring 3000 pts in GB6 at 5 GHz, that puts it right about 20% higher PPC in GB6. We previously had a range of ~17% - 25% PPC from previous leaks so this fits in with those prior scores.
I think GR and Strix will do just fine against ARL. It's just us geeks having too high of expectations form AMD, they spoiled us with previous Zen iterations.
I'm not concerned with how it performs against ARL, just trying to figure out what the heck AMD did with a core that is >20% bigger (includes L2 so the core without L2 is even bigger than that) but allegedly cut down on execution resources and didn't actually increase SIMD width. . . Something's not adding up.
Is the "A0 silicon" phrase the new "wait for the new Navi 31 revision"?They are selling their A0 silicon, wich say that they were pressed to release the chip as soon as possible, as for up to 6 months with no competition they can make a lot of money out of DT Zen 5.
Beside they are suley more concentrated in their mobile offerings, that s where there s actual competition and bigger volumes, so better to get rid of the DT parts and concentrate on the few mobile chips that are still under developpement like KRK and Strix Halo.
Well, one shouldn't trust any figure/pic given by AMD marketing dept. Just wait for the HotChips slides...Something's not adding up.
ESs are stepping 0, and they look to be good enough as to not requiring any revision, indeed that close to launch it s surely months that they are ramping the things.Is the "A0 silicon" phrase the new "wait for the new Navi 31 revision"?
Cezanne also went to prod at A0. Strix might have been lucky too.
As for Granite, do you have link pointing to a A0 being the prod revision? Since there were at least two revisions spotted - old 00B40F00 and new 00B40F40.
That AIDA bench shows Granite B0, am I reading that right?ESs are stepping 0, and they look to be good enough as to not requiring any revision, indeed that close to launch it s surely months that they are ramping the things.
So A0 silicon in this case is rather synonymous of early launch, reduced costs of developpement and finaly somewhat higher profits, the sooner the better for their bottom line.
We don't know the core size in STX (if it is different). Only the size of Granite Ridge (from the size of the CCD.If STX is not actually 512b wide FP then why did they double the cache bandwidth and why is the core so much bigger?
If STX is scoring 3000 pts in GB6 at 5 GHz, that puts it right about 20% higher PPC in GB6. We previously had a range of ~17% - 25% PPC from previous leaks so this fits in with those prior scores.
There’s a die image of strix, core size is the same as GR, at least in my rough approximation.We don't know the core size in STX (if it is different). Only the size of Granite Ridge (from the size of the CCD.
What we don't know is anything about battery life, or gaming. For mobile battery life is king, and gaming is important. But if that the "handicapped" Zen 5 with really good battery life, and its 10% faster in these tests, desktop should be awesome. Server should be out of this world.
Let’s not get too hyped up. If battery life is king in mobile, lunar lake will win that this year.What we don't know is anything about battery life, or gaming. For mobile battery life is king, and gaming is important. But if that the "handicapped" Zen 5 with really good battery life, and its 10% faster in these tests, desktop should be awesome. Server should be out of this world.
So they went for multi-thread gains?
9.71% in SIR 2017.
"In this test, a single Zen 5 thread still performs like a 4-decode x86 core. But when we enable two SMT threads for testing, we can see that the throughput doubles, and the instruction throughput reaches 8 in the L1-L2 and even L3 ranges, and in the DRAM range it returns to the same normal level as Zen 4."
@SarahKerrigan you were onto something, I guess
9.71% in SIR 2017.
"In this test, a single Zen 5 thread still performs like a 4-decode x86 core. But when we enable two SMT threads for testing, we can see that the throughput doubles, and the instruction throughput reaches 8 in the L1-L2 and even L3 ranges, and in the DRAM range it returns to the same normal level as Zen 4."
@SarahKerrigan you were onto something, I guess
Yeah, because then some were on the +32% hype train.Interesting. When I suggested drastically higher SMT throughput as a possible origin of the rumored Turin numbers back on 3 June, it got immediately dismissed.
It is an ES so I'm still holding reservations.
9.71% in SIR 2017.
"In this test, a single Zen 5 thread still performs like a 4-decode x86 core. But when we enable two SMT threads for testing, we can see that the throughput doubles, and the instruction throughput reaches 8 in the L1-L2 and even L3 ranges, and in the DRAM range it returns to the same normal level as Zen 4."
@SarahKerrigan you were onto something, I guess
Would be ironic and a bit strange.It is an ES so I'm still holding reservations.
If it does turn out to be an SMT queen then that does explain everything.
But that was a dismissal in the "april-launched $1k 32% IPC Zen 5" era.Interesting. When I suggested drastically higher SMT throughput as a possible origin of the rumored Turin numbers back on 3 June, it got immediately dismissed.
In June?But that was a dismissal in the "april-launched $1k 32% IPC Zen 5" era.
It is just really strange, as it seems like a single thread cannot utilise all core resources, did AMD design what is effectively Bulldozer 2: Electric Boogaloo?Would be ironic and a bit strange.
AMD's SMT was already far better than Intel's.
AMD vastly improved it even more, while...
... Intel want to give up on SMT entirely?
Still, would be a questionable choice outside of servers as for most other things the ST crown is a huge seller.
Yep, ST is very important. All things considered a mid release on the mobile platform in regards to that. However +66%MT is no joke, there will be people who want that. But man was I looking forward to that M4 killer in ST and IPC. Can you imagine if that happened and if it did I bet AMD would spent more time in the keynote about Zen 5. After all they had time to compare the M4 NPU...Still, would be a questionable choice outside of servers as for most other things the ST crown is a huge seller.