That's utter nonsense.
Will you do all memory allocations so that they're 4KB page aligned? And will you ensure all your data structure sizes will be <4KB? Can't wait to see how you achieve that in real life. If you have to do so because your ISA is limited, it's a dead-end.
There isn't such a limitations involved. What that immediate size will make is that data localisation is effectively used. If code generates 8 data base pointers all data access stays within immediate range on those data pointers all that loop accessed data can be cached in 32KB 8-way L1 cache. Data prefetching also works best possible way as prefetchers usually won't cross pages boundaries. Allow some kind of scaling for those data access patterns and everything isn't so simple anymore. To make great ISA designers should make what they can to help to produce as efficient code as possible. That sure seem to be one design points of RV.