It just sucks that AMD got tricked into promoting Microsoft's garbage software.Windows-key + G --> "This is a game" keeps the program running on CCD0 (no scheduling issues)
Need updated Gamebar and AMD windows driver package with balanced powerplan to work properly
The supply of V-cache dies being a limiting factor, using two of them in a single CPU prevents the "birth" of another CPU.
Just to remind you 3D V-Cache product isn't the only one leverages SoIC, MI300 series also rely on it.We really don't know that to be the case. There has been 3 years of ramping of capacity, and V-Cache sales are still tiny. I really don't think capacity is a problem.
If capacity was still the bottleneck, meaning TSMC has only the capacity for SoIC stacking that is equal to AMD V-Cache sales, then TSMC can just as well scrap SoIC from there web side and give up.
Something TSMC is not doing...
Alternative (and far more plausible) theory is that AMD is demand constrained currently, in all its CPU products, not supply constrained.
Look on eBay:
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When the price difference between identical core count server CPUs due to V-cache is more than $2000, no way AMD is just gonna give away their V-cache dies. It also cuts into their server marketshare because people and even companies could start using the dual V-cache CPUs for their commercial workloads instead of investing in a server.
Just to remind you 3D V-Cache product isn't the only one leverages SoIC, MI300 series also rely on it.
IMO, there isn't dual X3D consumer cpu because marketing shenanigan.
Just to remind you 3D V-Cache product isn't the only one leverages SoIC, MI300 series also rely on it.
IMO, there isn't dual X3D consumer cpu because marketing shenanigan.
You don't need gamebar for this, there is https://github.com/cocafe/vcache-trayIt just sucks that AMD got tricked into promoting Microsoft's garbage software.
None I guess. But this is the reason I believe AMD is capacity constrained with regards to V-cache. If they had abundant supply, they would have a LOT more SKUs, like maybe so:By the way, is there a reason why 8 core die with V-Cache + 6 core die is not possible?
8 core vcache + 16 core 5c... in a laptop...By the way, is there a reason why 8 core die with V-Cache + 6 core die is not possible?
Possible and probable, the two frenemies. Good 8 core dies already have their place in 8-core and 16-core SKUs, meanwhile 6-core and 12-core SKUs do a good job catching all kinds of imperfect dies.By the way, is there a reason why 8 core die with V-Cache + 6 core die is not possible?
For the 7 good cores CCD, they are probably disabling one good core to use these for 7600/7600X.the same could probably be said about 7+7 or 5+5.
Like I said...For the 7 good cores CCD, they are probably disabling one good core to use these for 7600/7600X.
meanwhile 6-core and 12-core SKUs do a good job catching all kinds of imperfect dies.
AFAIK with previous Zen cpus, each CCD must be downcored by the same number of cores.None I guess
I'm not sure if two v-cache CCDs are needed at all.So there were some technical reasons behind the decision of having asymmetrical CPU. It the technical challenges (of clock speed regression) are overcome, then there is no longer reason to have a complicated asymmetrical CPU any more.
I recall adroc saying something to the effect that cache coherency issues would come into play with a single shared large L3 across both CCDs. Also, not even sure if they can do that single shared L3. There might be issues with that thin V-cache die spreading across the boundaries of the two CCDs.(unless there's a big single L3 chunk glued atop of both CCDs, with 16 slices formed common for both CCD ring-bus ?)
It's not much different from 7950x. The number of cases where 7700x is faster than 7950x is limited.I'm not sure if two v-cache CCDs are needed at all.
If we assume they managed to get the V-cache CCD Fmax equal to that of regular CCDs, you'll still end up with inter-CCD penalty (unless there's a big L3 chunk glued atop of both CCDs). Different CCD Fmax will make things even worse.
If two CCDs are placed very close and are restricted to run at the same frequency, idk why there should be any issues. Also, the cores are probably need to be arranged as close as possible to one of the chiplet edges.I recall adroc saying something to the effect that cache coherency issues would come into play with a single shared large L3 across both CCDs.
It's due to user threads not being able to execute code without the involvement of a kernel thread. The kernel thread is in control of allowing the user thread to execute. So there's a LOT of inter-thread communication going on and core to core latencies need to be low to reduce that communication overhead.I am puzzled why many reviews analyze core to core latencies, as if that was a common usage. Vast majority of communication is core to memory, or core to L3 to Memory.
The issue is Server chips that have more than 2 CCDs IMO. All this extra complexity, that only really helps desktop usecases with 2 CCDs, makes it really unlikely AMD would design something like that.If two CCDs are placed very close and are restricted to run the same frequency, idk why there should be any issues
That's the problem. It's working on data in the shared memory space and the different threads have to behave by communicating with each other so that one thread does not corrupt any other thread's data in that shared memory space.Most typical case is that a thread mostly uses its own data, and typically, it does not jump from CCD to CCD.
Not really, it depends on application. The data I have been working on have large chunk of data for each thread. There will not be any inter process communication until the work is completed.It's not possible to achieve those highlighted requirements without constant inter-thread communication.