Tin foil hat time - I don’t think the 32% number was ever real. I think it was an honest mistake from extrapolating results from what appeared to be legit benchmark scores.
We’ve seen multiple instances where benchmark software incorrectly reports Zen 5 clocks much lower than it’s actually running. We’ve made this same mistake in this thread with Strix GB6 scores. I think this same thing happened with SIR2017 last year and it accidentally spawned a year long hype cycle.
9654 retail only does 2.5 ghz when all cores are loaded, where the 9554 does 3.5 ghz with all cores loaded, so it should be easy to get fairly decent higher clocks out of Turin.SPEC doesn't attempt to detect clock speeds itself (though it has a bunch of other very handy hardware-detection mechanism) so nah.
AFAIK the whole thing came from some people seeing something that said 96c Turin does 50% higher perf than 96c Genoa, without specified clocks, and started extrapolating it in the most hypey way imaginable.
9654 retail only does 2.5 ghz when all cores are loaded, where the 9554 does 3.5 ghz with all cores loaded, so it should be easy to get fairly decent higher clocks out of Turin.
Well, I think it could be related.....In fact ST int of plus 32% would mean a lot more MT, so lets see.Which is great and all, but irrelevant to what I was saying, which is that somehow "+50% socket throughput" transformed into "absolute confidence in +32% iso clock ST int" (and deliberate suppression of materials against that narrative.)
AFAIK the whole thing came from some people seeing something that said 96c Turin does 50% higher perf than 96c Genoa, without specified clocks, and started extrapolating it in the most hypey way imaginable.
Inferring anything with zero information about what is being tested is crazy. If it was limited by bandwidth and the platform got 50% more bandwidth you'd see that gain without the CPU core changing. If it was limited by SIMD and it got 50% more SIMD throughput, you'd see that gain but it would say nothing about what happens with ordinary real world code.
There are so many potential bottlenecks in a 96 core system I couldn't even list them all. Trying to infer IPC or ST gains from that is like trying to infer world population growth based on Super Bowl viewership.
Since I have both a 64 core and a 96 core Genoa, and see up front the differences, I see temperature/heat per sq inch a big reason for the differences in speed. With a new design and new arch, Turin may have distinct advantages. They are all using SP5 heatsinks and all are 12 channel memory.Inferring anything with zero information about what is being tested is crazy. If it was limited by bandwidth and the platform got 50% more bandwidth you'd see that gain without the CPU core changing. If it was limited by SIMD and it got 50% more SIMD throughput, you'd see that gain but it would say nothing about what happens with ordinary real world code.
There are so many potential bottlenecks in a 96 core system I couldn't even list them all. Trying to infer IPC or ST gains from that is like trying to infer world population growth based on Super Bowl viewership.
But there was, a lot.with zero information about what is being tested is crazy
it's SIR2017.If it was limited by bandwidth and the platform got 50% more bandwidth you'd see that gain without the CPU core changing. If it was limited by SIMD and it got 50% more SIMD throughput, you'd see that gain but it would say nothing about what happens with ordinary real world code.
Not really?There are so many potential bottlenecks in a 96 core system
But there was, a lot.
it's SIR2017.
Not really?
This isn't 2005, we're pretty good at multicore designs.
Yea, rate n.It was int_rate 2017 with nT base copies, no?
Oh I never said it was 1t (I think?).And you extrapolated that to 1t in what turned out to be, shall we say, an optimistic manner?
Yea, rate n.
Oh I never said it was 1t (I think?).
But AMD 1t gains are usually higher than their nT bumps (especially on major tocks), so there's that.
From memory 25% more power was specified. And the 50% increase was for the nT SpecInt.AFAIK the whole thing came from some people seeing something that said 96c Turin does 50% higher perf than 96c Genoa, without specified clocks, and started extrapolating it in the most hypey way imaginable.
looking at the image he has SMT off ? Core effective clocks should have T0 and T1 if SMT is on.View attachment 102572
7950X, stock + EXPO 6000C30. Set to 60W PPT (validated enforcement in HWINFO). Blender v3.3.0 benchmark. Seems off the 9950X would be slower by a fair amount, around 10% here.
As if I needed more reason to believe this guy is just screwing with us by doing weird configs that make no sense and no one would do in real life then not providing all the relevant information about it.looking at the image he has SMT off ? Core effective clocks should have T0 and T1 if SMT is on.
yeah fair call,As if I needed more reason to believe this guy is just screwing with us by doing weird configs that make no sense and no one would do in real life then not providing all the relevant information about it.
Seriously, who disables SMT, uses PBO+CO but tunes PPT down to 60W while using a custom waterloop? And then arbitrarily chooses a random older blender benchmark version?
If the HWInfo in that screenshot is accurate he's only getting ~25W core power. I reapplied my tuned 6400/2133 config that involves increasing several voltages to bump my misc and soc power but I was still getting 27-29W core power. My increased core power would explain some of the difference.yeah fair call,
even with a 1.25x multi to the score its "poor" uplift compared to your score.
Ever heard of Snapshot CPU Polling in hwinfo for Zen cpus ?looking at the image he has SMT off ? Core effective clocks should have T0 and T1 if SMT is on.
This option works on AMD Zen-based CPUs only.
When enabled, a snapshot of the entire CPU package and state of all its cores is read at once. This is different from the traditional approach when each core/thread determines its individual state (clock, voltage, etc.), which might cause it to interfere with the actual state. Hence, this polling mode does most accurately reflect the actual CPU state by eliminating the "Observer Effect" to a minimum.
Note, that in this mode some (i.e. per-thread) values might not be available.
Yea, that's got CPUs generally work.always lower than the 1t bump
?not immediately related, but aged like milk!)
Yeah, fat socket bumps are fat socket bumps.combined with your post immediately below, where you said that you considered "fat" to mean 40%)
you mean like this from the Zen 3 APU i am currently typing on:Ever heard of Snapshot CPU Polling in hwinfo for Zen cpus ?
HWiNFO v6.35-4310 Beta released
HWiNFO v6.35-4310 Beta available. Changes: Enhanced sensor monitoring on ASUS H570, B560, H510 and Q570 series. Added reporting of Precision Boost Clock Limit and Automatic OC Offset on AMD Vermeer. Fixed monitoring of CPU power and HTC status on AMD Zen3. Improved support of Intel Alder Lake...www.hwinfo.com
We've got GCC patches confirming 6 ALU pipes.Does anyone still believe that Zen 5 has more than 4 ALUs? The leaks so far suggest that even the 16% IPC gain seem to be a little bit too optimistic.
Is there a launch date given or is it still just "july" for Granite Ridge?