Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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Apr 1, 2022
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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E012 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15



Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



 

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511

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Jul 12, 2024
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Intel sucks on mobile for this very reason. The whole company has been in the mindset of highest performance transistors for 30 years.

Therefore it is natural that at the peak clocks, Intel processes are better. But in Lunarlake and Server products, TSMC is better.
At least they admitted it themselves and have focused on Mobile Process as well with 18A Intel 3 looks fine to me in servers with SRF we will see with GNR vs Turin both are 128C/256T btw Intel 7 sucks as a 7nm class node Too expensive and power hungry
 

mikk

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May 15, 2012
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Panther Lake is running windows.

Lunar Lake, our next generation AI PC, which achieved production release ahead of schedule in July, will be the next industrywide catalyst for device refresh. Lunar Lake delivers superior performance at half the power, with 50% better graphics performance and 40% more power efficiency versus the prior generation.

On Intel 18A, we released the 1.0 PDK (Process Design Kit) last month and are on track to be manufacturing-ready by the end of this year with production wafer start volumes in the first half of 2025. Panther Lake for client is now running Windows and looking very healthy. This is the first microprocessor to use RibbonFet, PowerVia and advanced packaging, achieving a significant milestone.
 

Geddagod

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Dec 28, 2021
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Not with Royal Core cancellation and reduction of R&D for design.

Nova Lake might be good, but Intel won't survive off one-hit wonders.
You are prob right, I just really wanted an excuse to use the "we are so barrack" meme.
So basically delaying royal core but using it
Splitting apart many royal features across many generations of cores piece by piece. And, tbd to see how many royal features are actually going to end up in the final cores. According to Exist50 at least, but that dudes been right countless times before soooooo
Since when royal core got cancelled?
apparently a monthish ago. Interestingly enough, seems like a couple people from Intel's advanced architecture group have also started leaving Intel at a similar timeframe, there's even a website for a startup with ex-Intel AADG employees lol
 

jdubs03

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Oct 1, 2013
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At this point I do think Nova Lake has to be the next big thing. Ground up architecture redesign plus 14A. Panther Lake seems okay, but it’s not going to be enough. Nova needs to impress.
 

Goop_reformed

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Sep 23, 2023
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apparently a monthish ago. Interestingly enough, seems like a couple people from Intel's advanced architecture group have also started leaving Intel at a similar timeframe, there's even a website for a startup with ex-Intel AADG employees lol
Weird. A certain Twitter user had a conversation with me about the Snapdragon X-Elite cloockspeed nearly two months before the semiaccurate article was published. This person also informed me about various Intel shenanigans, but the cancellation of the Royal Core was not among them.
 

Geddagod

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Dec 28, 2021
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Panther lake is the first processor with ribbonFET and PoweVia (meaning 20A has neither)

Bruh bruh bruh bruh
At this point I do think Nova Lake has to be the next big thing. Ground up architecture redesign plus 14A. Panther Lake seems okay, but it’s not going to be enough. Nova needs to impress.
NVL doesnt look like it will have a grounds up arch redesign.
Also isn't 14A supposed to be HVM in 2027? Am I tripping?
I suspect NVL is gonna be 18A or some variant of that....
Weird. A certain Twitter user had a conversation with me about the Snapdragon X-Elite cloockspeed nearly two months before the semiaccurate article was published. This person also informed me about various Intel shenanigans, but the cancellation of the Royal Core was not among them.
/shrug
 

SiliconFly

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Mar 10, 2023
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NVL doesnt look like it will have a grounds up arch redesign.
Also isn't 14A supposed to be HVM in 2027? Am I tripping?
I suspect NVL is gonna be 18A or some variant of that....
14A will be manufacturing read in late 2026. Not sure whether it’ll be ready in time for NVL considering the timeframes. It’s possible NVL will do a limited launch in 2024Q4 with volume later next year.

Or it might be on 18A-P considering it covers DT parts too.
 

jdubs03

Senior member
Oct 1, 2013
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I suppose it could still be 18A or a revision of that for late 2026/early 2027.

Do we have enough info on if Nova is not a redesign? Seems ambiguous at best.

If it’s not, Zen 6 will likely be well ahead in performance and availability. How is Intel going to catch up?
Lunar Lake needs to be close to Z5, and idk if they will be in perf.

But if they want to lead in 1T/nT and have similar efficiency as Z6/7, something big seems necessary.
 

AMDK11

Senior member
Jul 15, 2019
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In one of the videos presenting LionCove, Intel reveals that the future generations will have up to 8 FPU ports and 10 ALU ports.

I know I'm simplifying, but I suspect that the next generation will be a 10-way decoder, 6 FPU ports and 8 ALU ports.

Only the next one will introduce a 12-way decoder, 8 FPU ports and 10 ALU ports.
This assumption is reasonable.

Edit:
I would be cautious about any leaks about "Royal Core". It has been said for a long time that the implementation of "Royal Core" was divided into stages. According to this division, the first stage was to be a redesigned LionCove.

Just like AMD. Zen5 is the first redesigned generation, which is the basis for the development of subsequent generations. Now AMD is learning a new base for the development of future generations.

know my imagination has gotten carried away more than once when it comes to RedwoodCove and LionCove, but we have to face the truth. Zen 4 is not Bulldozer and GoldenCove is not Netbrust (microarchitecture). Such IPC jumps as with Conroe or Zen1 will not happen again.

In the case of IPC, to achieve an average jump of +30-40%, the core would have to be much more advanced than we currently see, and this is not profitable for either AMD or Intel, because such a huge expansion will not be compensated by the new lithographic process. Not to mention the required design time.

I don't think they will start using only 1-2 "huge" cores in their processors.


The breakthrough is not really a huge leap in IPC, but the breakthrough is a new microarchitecture that is intended to enable consistent IPC gains for subsequent generations.

The rest are fantasies straight from fairy tales about mosses and ferns.
 
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DavidC1

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Dec 29, 2023
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Edit:
I would be cautious about any leaks about "Royal Core". It has been said for a long time that the implementation of "Royal Core" was divided into stages. According to this division, the first stage was to be a redesigned LionCove.
Do you know who said Royal Core is a project and it would be done over "stages"?

MLID.

Do you know who said it wasn't?

Exist50, who has been consistently right, because that's what happens when you have ACTUAL sources.
Zen 4 is not Bulldozer and GoldenCove is not Netbrust (microarchitecture). Such IPC jumps as with Conroe or Zen1 will not happen again.
Right, because Apple/ARM does not exist.
 

AMDK11

Senior member
Jul 15, 2019
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Do you know who said Royal Core is a project and it would be done over "stages"?

MLID.

Do you know who said it wasn't?

Exist50, who has been consistently right, because that's what happens when you have ACTUAL sources.

Right, because Apple/ARM does not exist.
Time will tell which side is the truth. At this point, it's just speculation for me.


Did Apple design M1 with a market like Xeon or Epyc in mind where the number of cores matters? Let me know when Apple achieves an average 30% IPC increase again.

To simplify:
Core Everest(Apple M4)
L1-I 192KB 6-Way
10-wide decode
ROB 918
8x Exec ALU
4x Exec FPU
2x SD
5x AGU(3x Load + 2x Store)
L1-D 128KB 8-Way

Core LionCove
L1-I 64KB 16-Way
8-Wide decode
12-Wide UOP cache 5248
Dispatch 8-Wide
ROB 576
6x Exec ALU
4x Exec FPU
2x SD
6x AGU (3x Load + 3x Store)
L0-D 48KB 12-Way
L1-D 192KB

Core Zen 5
L1-I 32KB 8-Way
2x 4-Wide decode
12-Wide UOP cache 6000
Dispatch 8-Wide
ROB 448
6x Exec ALU
4x Exec FPU
4x AGU (4x Load/2x Store)
L1-D 48KB 12-Way

I have a strange impression that AMD and Intel have reached an agreement regarding part of the microarchitecture. Like: You and I will have an 8-Wide decoder, 6x Exec ALU, 4x Exec FPU and we'll see which one is better.

Damn, they even agreed on the ALU issue - 3x multiplication and 3x Branch.

But this is just a coincidence XD
 
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Geddagod

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Dec 28, 2021
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Did Apple design M1 with a market like Xeon or Epyc in mind where the number of cores matters?
what exactly about Apple's core design makes it unsuitable for servers? If anything, large core-private caches would be better suited for server workloads since they would be able to deal with mediocre memory and L3 latencies better. The area of their cores are not bad either. They excel at lower power, much like a server core should.
Time will tell which side is the truth. At this point, it's just speculation for me.
Doubt. Why would Intel ever talk about a canned project? It's been ages since Ocean Cove got canned, and we don't have anything on it either. I think the most anyone would ever get it whispers from people connected to the project, and that's pretty much it.
 

AMDK11

Senior member
Jul 15, 2019
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what exactly about Apple's core design makes it unsuitable for servers? If anything, large core-private caches would be better suited for server workloads since they would be able to deal with mediocre memory and L3 latencies better. The area of their cores are not bad either. They excel at lower power, much like a server core should.
The Firestorm core consists of several large cores on a single board. They could afford the L1 monster and a more complex, low-clock core. They had no competition, so they developed without pressure.

AMD and Intel consider Xeon and Epyc when designing to accommodate a certain number of cores, as well as those designed for higher clock speeds. So there is less room for improvement as clock speed and core complexity always lead to trade-offs.

By the way, is there a table or graph of the average IPC increases for the FP and INT of Apple's big cores from each Mx generation?
 
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