Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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sl0519

Member
Aug 10, 2024
32
86
51
No link to the review..?

This 9700X curve can be right only if the idle power is much higher than the one of the 7700X, hence the apparent low efficency at low power, as said provide us a link so we can chek what it is about.

I posted it last page but I will post it here again.
His screenshot is taken from 7:04


Zen 5 is basically in parity with Zen 4 going below 75W. There's the answer.

This guy also briefly mentioned the fact that DDR5-6000 is crippling Cyberpunk 2077's performance.
 

Timmah!

Golden Member
Jul 24, 2010
1,521
852
136
All you armchair experts saying Zen5 stinks at gaming, explain the .1% lows away


View attachment 104986
View attachment 104987
View attachment 104988
View attachment 104989
Are there any gaming tests spevifically with RT on, in games like Cyberpunk or Those spiderman games, or control…. I recall there were people here who claimed this was achilles heel to Zen4, the vanilla ones at least, compared to Intel, so it would be good to see if there is any improvement.
 

Abwx

Lifer
Apr 2, 2011
11,591
4,408
136
I posted it last page but I will post it here again.
His screenshot is taken from 7:04


Zen 5 is basically in parity with Zen 4 going below 75W. There's the answer.

This guy also briefly mentioned the fact that DDR5-6000 is crippling Cyberpunk 2077's performance.
Thanks for the link.

There s the run at 88W where each core is at 6-7W, if we round this number to 7W this amount to 56W cores power and about 30W uncore power, wich is very close to Hardwareluxx 27W idle power when PBO is enabled.

Given that the 7700X idle power is 12-14W (depending of the MB) that explain why the 9700X curve at lower power is below the former s one.

 

Hail The Brain Slug

Diamond Member
Oct 10, 2005
3,525
2,493
136
Problem is that Computerbase has this for CB 2024, someone said that it could be the cores power wthout the uncore but from the 7950X review it s clear that they measure the whole package power.
PPT limit of the 7950X is 230W and under sustained heavy MT workloads, it tends to sit around 215-225W due to hitting thermal limits (vs. Sitting closer to or hitting 230W PPT limit). The graph appears to show ~200W, which seems like it would be in the neighborhood of core only power.
 

Rheingold

Member
Aug 17, 2022
64
170
76
Problem is that Computerbase has this for CB 2024, someone said that it could be the cores power wthout the uncore but from the 7950X review it s clear that they measure the whole package power.
That someone was me. And yes, they usually measure package power, but for that specific measurement they only measured the cores. It's described in the text. How about just using auto-translate:



And yes, I still need to point out the "four cores" mistake to them. That's 8 cores for all the lines.
 
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Abwx

Lifer
Apr 2, 2011
11,591
4,408
136
PPT limit of the 7950X is 230W and under sustained heavy MT workloads, it tends to sit around 215-225W due to hitting thermal limits (vs. Sitting closer to or hitting 230W PPT limit). The graph appears to show ~200W, which seems like it would be in the neighborhood of core only power.
No, there s peaks over 200W, beside the CPU use only 189W in Handbrake wich is the app used for this test and 196W in Prime 95, from their measurement at the main power in Cinebench can be estimated accurately at 215W peak at most.
That someone was me. And yes, they usually measure package power, but for that specific measurement they only measured the cores. It's described in the text. How about just using auto-translate:

View attachment 105008

And yes, I still need to point out the "four cores" mistake to them. That's 8 cores for all the lines.

So the uncore use 30W like in the chinese review, wich is a lot for Cinebench, and as i already pointed that s the cause of the perf being mediocre relatively to the 7700 at low powers but eventually also at higher powers albeit to a lesser extent.
 

Geddagod

Golden Member
Dec 28, 2021
1,296
1,368
106
That someone was me. And yes, they usually measure package power, but for that specific measurement they only measured the cores. It's described in the text. How about just using auto-translate:

View attachment 105008

And yes, I still need to point out the "four cores" mistake to them. That's 8 cores for all the lines.
Wow that's mid. Again, I can not wait for that spec2017 int power curve lol.
 

Josh128

Senior member
Oct 14, 2022
463
744
106
It seems to be an architecture that is a bit big for its boots, or at the very least not optimised for the node. Reading between the lines in various interviews it did seem that's what Engineering would have liked exclusivity on N3E

View attachment 104985

This curve matches some of the data from early 9950X testing.




Seems the knee of the curve for Zen 5/N4X is both higher and less aggressive than Zen 4 on N5(p) It's easy to say N3E won't help much, but doesn't need much. Shifting that curve to the left is all. The fact it's still scaling suggests it really does need to be on a better node.


Still have to wonder why a higher TDP point wasn't selected for the 9700X , Is there voltage limit issues pushing higher TDPs on this node? it would also explain the max ST boost clocks pretty stagnant. Has anyone been able to push these higher yet?
This is exactly my thoughts. Zen 5 seems to have been architected to take advantage of N3, while simultaneously being designed to work on N4. Its quite odd, and as a matter of fact, I cant think of any other CPU that was simultaneously designed and released (yes, Turin not out yet released but running in labs and sampling) on two fully different process nodes.

Architectures are designed for certain transistor densities and power characteristics for a good reason. For example, Intel cant just port 10nm Golden Cove to 14nm and use a bigger die to compensate for larger sized process and get the same performance. You will see very undesirable and/or strange power and frequency characteristics and some cut corners on the larger node. We also know that a 16 core CCX design is part of the Zen 5 architecture, but, for reasons described above, will never see the light of day on 4nm.

I dont believe Zen 5 4nm is a "backport" per se, I believe it was done early on because AMD considered that N3 volume and pricing would very likely not be profitable for consumer desktop. Its also very possible that Intel, seeing their own process issues, pre-empted them and bought up the 3nm volume (they bought a LOT) that would have been needed for desktop and mobile Zen 5. Its going to be very interesting to see how Arrow Lake is priced when it releases. Just by looking at all the different process nodes and packaging tech it uses, on paper it should be the most expensive to produce consumer x86 CPU to date.

Its going to be very interesting to see how the 3nm, possibly 16 core CCX, Zen 5c performs on Turin, and also to see how Strix Halo performs, seemingly having completely different packaging and 3nm (?) uncore designs. Maybe it will have a new memory controller as well.
 
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Josh128

Senior member
Oct 14, 2022
463
744
106

Not very encouraging. Hopefully the EXPO 8000 MT/s kits will have lower timings than the ones for the kit used by Larabel.

I really want AMD to pull some miracle with an updated IOD that allows the X3D chips to use DDR5-8000 in 1:1 mode.
Not going to happen. Strix Halo might be able to do something like that with its 3nm IOD and new chiplet packaging, but its designed for LPDDR so I dont know if its even technically possible to release on a desktop package and work with DDR5.
 

sl0519

Member
Aug 10, 2024
32
86
51
This is exactly my thoughts. Zen 5 seems to have been architected to take advantage of N3, while simultaneously being designed to work on N4. Its quite odd, and as a matter of fact, I cant think of any other CPU that was simultaneously designed and released (yes, Turin not out yet released but running in labs and sampling) on two fully different process nodes.

Previously it is said that Arrow Lake simultaneously uses TSMC N3B for the higher end and Intel 20A for i5 non K and below. I'm not sure if this is still the case.
 

MS_AT

Senior member
Jul 15, 2024
311
691
96

Not very encouraging. Hopefully the EXPO 8000 MT/s kits will have lower timings than the ones for the kit used by Larabel.

I really want AMD to pull some miracle with an updated IOD that allows the X3D chips to use DDR5-8000 in 1:1 mode.
The reason why 8000MT is doing little to nothing is the number of GMI links. Single link is the bottleneck for throughput. So going with higher kits will make sense only for dual chiplet SKUs. And 1:1 mode is less important for x3D SKUs because they have the 3d cache to insulate from DRAM latency.
 

Asterox

Golden Member
May 15, 2012
1,039
1,824
136

Not very encouraging. Hopefully the EXPO 8000 MT/s kits will have lower timings than the ones for the kit used by Larabel.

I really want AMD to pull some miracle with an updated IOD that allows the X3D chips to use DDR5-8000 in 1:1 mode.
If you want to show off your memory, now or in the future you still have to buy a completely different AMD CPU. Latency or performance aside, a classic Zen4 or Zen5 CPU outside of the G series can't even move with 10600mhz DDR5 memory.

R5 8500G laughs and enjoys the beach!

 

biostud

Lifer
Feb 27, 2003
18,733
5,497
136
A

Not very encouraging. Hopefully the EXPO 8000 MT/s kits will have lower timings than the ones for the kit used by Larabel.

I really want AMD to pull some miracle with an updated IOD that allows the X3D chips to use DDR5-8000 in 1:1 mode.
If the redesigned core lets the 3D cache models run @ full speed 5.5Ghz then it will be ~15% better performance than the 7800X3D.
 
Jul 27, 2020
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Good information, y'all!

@MS_AT , thank you for filling me with hope for the 9950X with DDR5-8000 Can't wait to see the Phoronix benchmarks for that!

@Asterox , so DDR5-8000 kits will be more beneficial for Zen 5 desktop APUs!

From http://www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/:

In fact, the AVX512 improvement on Zen5 created a memory bottleneck so large that it became the primary reason why I promoted the BBP mini-program from a tool for verifying Pi records to a formal benchmark. The regular benchmarks wouldn't do Zen5 (and future processors) any justice. At least until someone can figure out how to get DDR5-20000 on AM5...

DDR5-20000 would have about 310 GB/s of bandwidth.

Guess which upcoming part has that much bandwidth on tap?

STRIX HALO!!!!

Now if AMD doesn't cut the AVX-512 width in that part, we are in for a REAL performance revolution!
 
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StefanR5R

Elite Member
Dec 10, 2016
5,968
8,941
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MS_AT

Senior member
Jul 15, 2024
311
691
96
Good information, y'all!

@MS_AT , thank you for filling me with hope for the 9950X with DDR5-8000 Can't wait to see the Phoronix benchmarks for that!

@Asterox , so DDR5-8000 kits will be more beneficial for Zen 5 desktop APUs!

From http://www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/:



DDR5-20000 would have about 310 GB/s of bandwidth.

Guess which upcoming part has that much bandwidth on tap?

STRIX HALO!!!!

Now if AMD doesn't cut the AVX-512 width in that part, we are in for a REAL performance revolution!
Just keep in mind, that you need both CCDs active to see the improvement in Mem BW. Because each CCD has only one active GMI link to IOD. But the CCD itself has two GMI interfaces [at least this was the case with Zen4 and this was a reason why some lower core count SKUs had 2 links enabled, to ensure they could better tap into socket's bandwidth].

Likewise for Strix Halo, what will be important is how many GMI links will be active as this will decide how much of the overall bandwidth CPU can use. I think Adroc claimed that 2 links will be active, but until they release the product we won't know for sure.
 

Heartbreaker

Diamond Member
Apr 3, 2006
4,347
5,471
136
Not going to happen. Strix Halo might be able to do something like that with its 3nm IOD and new chiplet packaging, but its designed for LPDDR so I dont know if its even technically possible to release on a desktop package and work with DDR5.

Generally most designs can work with LPDDR and DDR.

But not on AM5. Strix Halo needs 256 bit memory, so it needs 4 independent memory slots. AM5 is 128 bit.

Maybe some variation of Next generation Threadripper, could support a socket version of Strix Halo. But even then it would have less bandwidth than the laptop version.
 

Det0x

Golden Member
Sep 11, 2014
1,336
4,487
136

Not very encouraging. Hopefully the EXPO 8000 MT/s kits will have lower timings than the ones for the kit used by Larabel.

I really want AMD to pull some miracle with an updated IOD that allows the X3D chips to use DDR5-8000 in 1:1 mode.
Easiest and largest performance gain for AM5 is maxing tREFI out at 65k for all memoryspeeds
Sadly it seems like very few reviews understands t‍his 🤷‍♀️
 

Det0x

Golden Member
Sep 11, 2014
1,336
4,487
136
Seems like either windows 11 or nvidia drivers needs to update the thread scheduling for Zen5 (?)
That's at least my take on this data..
During the course of our testing, we observed that Windows 11 was scheduling workloads on the 9700X in a manner that would try to saturate a single core first, by placing workloads on each of its logical threads. Additionally, the placement would put load on the CPPC2 "best" or "second-best" core (gold and silver in Ryzen Master)—which makes sense. However, if a highly demanding single threaded workload runs on one core, scheduling another demanding workload on the second thread of that core will result in lower overall performance. It would be better to place them on two separate cores, where they each have access to the full resources of that core. We hence set out to see if this is an SMT-specific problem.










Don't think i've observed this behavior on my 16 core Zen5
 
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Jul 27, 2020
20,420
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Easiest and largest performance gain for AM5 is maxing tREFI out at 65k for all memoryspeeds
Sadly it seems like very few reviews understands t‍his 🤷‍♀️
I think I read in some online posts that higher tREFI can result in hotter DIMMs. Is it possible to do 65536 tREFI without special cooling on DIMMs?
 

Hail The Brain Slug

Diamond Member
Oct 10, 2005
3,525
2,493
136
I think I read in some online posts that higher tREFI can result in hotter DIMMs. Is it possible to do 65536 tREFI without special cooling on DIMMs?
If anything, I'd think it would run the dimms cooler. All it does is increase the time between refreshes. Fewer refreshes = less power = cooler, maybe?
 
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