Ryzen 9K stepping is B0? So EPYC is a newer stepping?
And the massive L3 CacheMakes you think about what stepping the X3d parts will have...
Son of a.....!!!
We got leftover (buggy?) stepping!
Can you explain? I see 4.1 GHz at 1.01 V. How does that compare to Zen 4/Zen 5 desktop chiplet?You guys didn’t even notice the clocks in the screenshot, did you?
Oh, that's certainly a nice boost. I'm more interested in what clocks the X parts can maintain. Coupled with the I/O improvements with the recently noted kernel patch, those should be notably impressive.You guys didn’t even notice the clocks in the screenshot, did you?
Nothing…yet. However it is a considerable jump over Genoa and Bergamo. I know we had possible leaks, but screenshots are confirming it.Can you explain? I see 4.1 GHz at 1.01 V. How does that compare to Zen 4/Zen 5 desktop chiplet?
Well top-end 128C Genoa (the 9754) tops out at 3.1. This one has 4.1. Not sure if that's an all-core boost, but it's a significant gain from the clocks alone.Can you explain? I see 4.1 GHz at 1.01 V. How does that compare to Zen 4/Zen 5 desktop chiplet?
Well top-end 128C Genoa (the 9754) tops out at 3.1. This one has 4.1. Not sure if that's an all-core boost, but it's a significant gain from the clocks alone.
Which is interesting. Does B1 somehow have a massively better v/f curve compared to B0?
For one, we have no idea the %load of these 2, so its virtually meaningless. I have a 64 core Turin on the way, it will be here Friday, so I will update my Turin build thread at that time. (weel, after a couple of days to put it in)Can you explain? I see 4.1 GHz at 1.01 V. How does that compare to Zen 4/Zen 5 desktop chiplet?
That's Bergamo, not Genoa.top-end 128C Genoa (the 9754) tops out at 3.1
64c Genoa, if switched to cTDP_high = 400 W, reaches its f_max of 3.7 GHz in some lighter workloads on all threads. Extrapolating from that, 128c Turin might run at 4.1 GHz with similarly light workloads on 50% of the SMT threads, as a guess.This one has 4.1. Not sure if that's an all-core boost, but it's a significant gain from the clocks alone.
"We", as in "the unwashed masses", don't know that. The regression of the concurrent CMPXCHG microbenchmark may or may not be connected with the area reduction of on-CCD L3$. ("We" are still in the dark how AMD achieved this reduction.) Stacked cache removes area constraints, so there is that. But I doubt that stacked cache would be used to reintroduce performance related functionality which was perhaps (or perhaps not) cut from the on-CCD cache.Do we know if the X3D cache will help with the added inter-core and inter-CCD latency in Z5?
Can we give you a long list of benchmarks to run on it or are you going to put it immediately to DC work as you typically do?I have a 64 core Turin on the way, it will be here Friday, so I will update my Turin build thread at that time. (weel, after a couple of days to put it in)
One of the first benchmarks will be 8 8C tasks (thats 64 threads used, and lasso disables SMT for this, so all the CCD cache can be used by one process), then cb 24, then only those that I have free access to.Can we give you a long list of benchmarks to run on it or are you going to put it immediately to DC work as you typically do?
If it's the running part that's hard for you (because all that waiting for benchmarks to finish can test anyone's patience), would you be willing to let some trusted member here login to your machine remotely and run benchmarks for a couple of days before you get your DC workloads running?
Thanks for the correction, I completely forgot that Genoa topped out at 96C.That's Bergamo, not Genoa.
64c Genoa, if switched to cTDP_high = 400 W, reaches its f_max of 3.7 GHz in some lighter workloads on all threads. Extrapolating from that, 128c Turin might run at 4.1 GHz with similarly light workloads on 50% of the SMT threads, as a guess.
| AMD EPYC 9555 | Zen 5 | 64 / 128 | 256 MB | 3.30 GHz | DDR5-6000 | 360W |
| AMD EPYC 9535 | Zen 5 | 64 / 128 | 256 MB | 3.50 GHz | DDR5-6000 | 300W |
So Turin will use 12 channels of "sweet spot" DDR5-6000???Its one of these 2, specifically this part number
100-000001247-12 part
AMD EPYC 9555 Zen 5 64 / 128 256 MB 3.30 GHz DDR5-6000 360W AMD EPYC 9535 Zen 5 64 / 128 256 MB 3.50 GHz DDR5-6000 300W
On the screenshot you can see that it is 2 socket configuration with each socket having 128 cores with SMT disabled. So this frequency doesn't have to be anything special64c Genoa, if switched to cTDP_high = 400 W, reaches its f_max of 3.7 GHz in some lighter workloads on all threads. Extrapolating from that, 128c Turin might run at 4.1 GHz with similarly light workloads on 50% of the SMT threads, as a guess.