Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

511 · Aug 31, 2024

What they need is Andy Grove i have heard in 80s when they were shifting from memory to microprocessor he personally went and asked some senior people if they are with him or not one guy said No and he fired him on the spot the next guy said yes

jur · Aug 31, 2024

What does 24 wide issue even mean? 24 wide decode?, 24 wide execution?, 24 muOps from muOp cache to execution? Dividing larger core to multple smaller cores is quite insane idea. How would that work, what would be the latency to switch? How would private caches divide and what would happen to data in those caches? And 2x ipc at 5.5ghz? At what power? The ideas thrown around here are like Jensen's "beyond the limits of physics"

DavidC1 · Aug 31, 2024

jur said:
What does 24 wide issue even mean? 24 wide decode?, 24 wide execution?,

Yes, 24-wide decode. That's the accepted term, kinda like secret code some people and groups have among theirs but outsiders are confused about.

I agree about sounding insane too. In some ways if Pat was responsible for cancelling it, it makes sense.

What is stupid is diverting them to "AIeee" teams. Corporate version of FOMO. If Pat was responsible, then it understates some saying he's out of touch. How can you be so stupid as a former microprocessor engineer?!

DavidC1 · Aug 31, 2024

cannedlake240 said:
The AI hype might end any time now while Client & DC CPUs aren't going anywhere

Saying they missed the AI hype is looking just at the surface level. It really showcases how lazy, out of touch the whole company was. The "writing was on the wall" 30 years ago.

Like I mentioned before, Intel was fat and lazy soon after the original three founders stopped leading the company.

-Read the article behind Intel's Celeron. They wouldn't have had Celeron without Dell wishing to have lower cost CPUs. So that's how Cyrix got traction, and of course AMD. It isn't just lazyness, it is elitism. Oh only people with $3000 to spend should get computers.
-Pentium M was inspired out of Transmeta's Crusoe. Had some fantastic news about that CPU. Half the cost laptops with twice the battery life, something like that.
-Core 2 wouldn't have been developed without AMD's intense pressure.
-Lunarlake wouldn't have existed without Apple leaving them!

How can an engineering company of Intel's size not see those things coming? With passion for electronics wouldn't you think "ah this is a natural way of going about things"? Make computers more widespread and popular for people by making it, smaller, cheaper, and lower power?

I started reading about CPUs in 1998. Not since that time were they ever proactive about new markets. It was always follow the FAD. The ideological problems for Intel really lies there. Without it, they'll keep missing future FADs too.

By the way Reddit is saying Intel stayed with four cores because the executives saw no reason for more when AMD was nowhere near them. Now at this point I hope some realizes why I think the E core design/team that changes architecture drastically every generation and P core team doing it a wee bit at a time is a huge problem and destined to meet it's end.

jur · Aug 31, 2024

DavidC1 said:
I agree about sounding insane too. In some ways if Pat was responsible for cancelling it, it makes sense.

It's not just insane, there are some claims in there that just don't make sense - big red flags. Like merging P and E cores. P and E are made for a completely diferent power envelope. Merging them would create what? A core that is best in both envelopes at the same time?

DavidC1 said:
What is stupid is diverting them to "AIeee" teams. Corporate version of FOMO. If Pat was responsible, then it understates some saying he's out of touch. How can you be so stupid as a former microprocessor engineer?!

"Aleee" teams? Could you explain? Imo, it's completely normal that people move among projects. Some projects end, are scraped,.. whatever, it happens in every company. Of course you can argue about scraping certain project,.. but this is pointless, since we don't have enough info. Where I work, people always get asked what they would like to work on and their wishes are taken into account as much as possible. Moving people to where company needs them is the only sensible thing.

DavidC1 · Aug 31, 2024

jur said:
It's not just insane, there are some claims in there that just don't make sense - big red flags. Like merging P and E cores. P and E are made for a completely diferent power envelope. Merging them would create what? A core that is best in both envelopes at the same time?

Those are MLID claims. I'm talking about 2x or 3x over Raptor Cove claims.

jur said:
"Aleee" teams? Could you explain? Imo, it's completely normal that people move among projects.

Let me ask you. What is the current FAD? That's where Intel moved the AADG(Royal Core) engineers to. To chase the FAD. It's a questionable decision if you are among the early ones. But doing that now when you are basically in the last place?

Are you saying you don't understand the concept that top engineers working on their dream project wouldn't feel offended by shifting to current FAD?

They did the same thing with the mobile boom. They sacrificed their main process to boost mobile chips which ultimately ended up in total exit of the market anyway. Remember the 3770K and 4770K being minor advancements over predecessors? Because the entire 22nm process was meant to boost Atom, at a sacrifice of desktop.

Those decisions are likely still felt today.

Thunder 57 · Aug 31, 2024

I wonder what happens to these companies when the AI bubble pops. It will surely hurt Nvidia but they have already cashed in on it. AMD is getting some money now too. Intel might just miss the boat. That is assuming there is an AI bubble, which I think many of us think does exist.

jur · Aug 31, 2024

DavidC1 said:
Let me ask you. What is the current FAD? That's where Intel moved the AADG(Royal Core) engineers to. To chase the FAD. It's a questionable decision if you are among the early ones. But doing that now when you are basically in the last place?

Let's first clarify what FAD is. My understanding is that FAD is technology that is created without a meaningful intent to solve a particluar problem.
Intel has some FADs: neuromorphic computing, quantum computing, silicon photonics research group.
Maybe I missed something, but I thought Intel is moving engineers to GPU development, which in my opinion makes sense. Intel absolutely should develop GPU hardware and oneapi. I think it's a promising alternative to Cuda. If it's worth it and whether they can actually become competitive is another matter. I certainly hope so.

OriAr · Aug 31, 2024

Philste said:
I'm not sure Royal Core was ever real. Also these MLID Leak from today is so weird again. So he really wants to tell us that Intels Flagship 2028 product would've been 6(!) Cores?!? Even with the claimed double IPC that would mean Intels 2028 Product would have same MT than their 2022 product, that makes no sense. 6 of those Cores would never be a highend part in 4 years, even if they can split up to 24 Threads.

Royal Core was real, and the reason it got canned is pretty simple, Intel realized they had no chance whatsoever of hitting its performance targets with it, regardless of the node.
It'd have also meant maintaining 3 different lines of cores as the Coves were still gonna be used on servers.

lightisgood · Aug 31, 2024

Falkentyne said:
Intel is in their situation because of BAD leadership the last 20 years.
Use inline Google translate.
Gel made mistakes, sure, but he isn't the primary cause.

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eetimes.itmedia.co.jp

I well know technical writers in Japan.
Frankly speaking, he is incompetence.

DavidC1 · Sep 1, 2024

lightisgood said:
I well know technical writers in Japan.
Frankly speaking, he is incompetence.

That depends on the individual just like everything and everywhere.

Hiroshige Goto at PCWatch knew what he was talking about.

jdubs03 · Sep 1, 2024

In response to MILDs post about Royal Core. As always some salt is needed.

ondma · Sep 1, 2024

coercitiv said:
Let's play a game, I'm the golden trickster fish and you're Pat Lucky. You found me while fishing, and you get one wish to save Intel from the ones below:

Intel gets best SoC of 2025 with Lunar Lake and Arrow Lake wins vs. Zen 5 in performance and efficiency (ARL refresh included)

Intel matches or beats TSMC with their fifth node in 4 years, and is set to win foundry contracts for short and mid term

Why am I the trickster golden fish, you ask? Because when you pick one, the other is automatically excluded. In a way this matches reality, it would take a miracle for both of the above to happen at the same time. So which one do you pick to save Intel? 🐡

How about if neither happens? Honestly, that IMO is the most likely scenario. As for 1, LL may be the best windows SOC for its intended niche, and if it is, that would be a win. Those that think it is somehow going to beat Apple are just dreaming, and it is a niche product that is not going to turn the company around. I also dont see ARL beating Zen 5 (or even Zen 4 since they seem to have similar performance). Zen 5 being basically a dud left a huge opening for Intel, but the new optimizations are making Zen 4 and 5 much more competitive. For gaming, I hope ARL will be competitive with Zen 4/5 and "just work" without all the diddling around that it seems to take for Zen (right build of windows, PBO, "enhanced" PBO, etc).

As for #2, no matter how "good" the nodes are technically, hell, they cant even make enough wafers to supply their own products, much less become a foundry.

ondma · Sep 1, 2024

SiliconFly said:
I beg to differ. I think the name royal core might even be imaginary. And the term rentable units might have been cooked-up by one of the so called leakers. But the concept is real & Intel working on it was real. It was even confirmed by Dr. Ian Cutress. And comparing timelines, it's evident it was Jim Keller's baby during his time at Intel. Not sure about it's current state.

It's even clear from MLID's video where he says he asked keller "how to combine multiple threads to make a single thread to boost IPC". Stupid question. He says keller replied it's actually the opposite which is very true. I'm actually appalled by MLID's ignorance. If he can't grasp such basic concepts, we need to question each & every assessment he makes based on his leaks.

Just to clarify:

Hyper-threading (HT) is running multiple threads in a single core. Generally speaking, HT makes a single core appear as 2 cores to the OS to facilitate efficient multi-threading.

Rentable Units (RU) on the other hand is simply running a single thread simultaneously on multiple cores. A single thread is sliced into multiple smaller threadlets, and all threadlets are simultaneously executed using multiple physical RU cores (and/or virtual RU cores according to implementation).

It was supposed to be the holy grail of ST performance uplift. And Intel clearly had it within its grasp without a doubt. And for heaven's sake, when they acquired it, the proof-of-concept implementations was into 3rd generation. Meaning, very mature and very real. And now thanks to the 3rd knucklehead Pat, it appears it's cancelled or postponed or split into pieces and added incrementally into products. I'm starting to getting a feeling we may never see proper RU in the near future.

You may be correct, I dont really know. But if RU is this magic technique, why dont we hear anything about it from AMD? They have plenty of resources to investigate new architectures now.

511 · Sep 1, 2024

ondma said:
How about if neither happens? Honestly, that IMO is the most likely scenario. As for 1, LL may be the best windows SOC for its intended niche, and if it is, that would be a win.

Lunar lake is niche but not niche as well it's like saying A macbook pro with M2/M3 is niche but it is worth it for majority of people

jdubs03 · Sep 1, 2024

ondma said:
You may be correct, I dont really know. But if RU is this magic technique, why dont we hear anything about it from AMD? They have plenty of resources to investigate new architectures now.

It’s a fair point. Seems like a no-brainer that each chip design company would have R&D projects focusing on such concepts if they offer true step-change performance potential. Hence buying AheadComputing is such an easy decision for anyone looking to burnish their chip design teams.

Doug S · Sep 1, 2024

DavidC1 said:
Royal Core version 1 was supposed to be a 24-wide issue one with novel ideas like Value Prediction and 2x perf/clock over Raptor Cove. The version 2 was supposed to be 3x.

See, this is how you know the whole thing was fantasy, or if it ever really existed that it was nothing like this.

No chance in the world that anyone takes a step from the 6/8/10 issue of today all the way to 24. Its completely ridiculous, there is not remotely that much parallelism to extract, you'd execute 24 instructions at once so rarely that the level of complexity could never pay back the huge increase in power consumption.

This is all a bunch of bs, if there ever was a "Royal Core" it sure as hell wasn't this. This is like saying that VW had some secret EV project that would get 1500 mile range out a battery half the cost of today's but still the same size and weight. You might want to believe it, but advancements don't happen like that.

Nothingness · Sep 1, 2024

Doug S said:
No chance in the world that anyone takes a step from the 6/8/10 issue of today all the way to 24. Its completely ridiculous, there is not remotely that much parallelism to extract, you'd execute 24 instructions at once so rarely that the level of complexity could never pay back the huge increase in power consumption.

Indeed. There's an average of 1 branch every 5 or 6 instructions, good luck trying to predict and resolve 4 ou 5 branches each cycle.

Also any claim of 2x perf/clock can't be taken seriously unless one starts from a very low performance point which is not the case here.

It looks like the derailed 40% hype train is already forgotten 😀

PS - Of course there are tasks that have large parallelism, but they are better left to more efficient units that don't need a complex and power hungry front-end.

naukkis · Sep 1, 2024

Doug S said:
See, this is how you know the whole thing was fantasy, or if it ever really existed that it was nothing like this.

No chance in the world that anyone takes a step from the 6/8/10 issue of today all the way to 24. Its completely ridiculous, there is not remotely that much parallelism to extract, you'd execute 24 instructions at once so rarely that the level of complexity could never pay back the huge increase in power consumption.

It's not traditional 24 issue cpu but 6 4-issue cores that can also combined to execute single thread. To do that they need register file interconnect network and complex front end that can split running thread effectively to different cores as there are additional latency when crossing split register file boundaries.

Actually what it is - Amd Bulldozer - AMD didn't implement integer register file interconnect in Bulldozer to being able combine both execution parts to single thread - they probably just failed trying after Keller left. Remember Keller's Alpha 21264 was split register file design with register file interconnnect but without smart front-end needing compiler or programmer effort to extract both cores power in single thread.

And Intel probably canceled design because it's massive 1T perf with massive power usage. Today such a design is useful only on niche markets.

511 · Sep 1, 2024

Nothingness said:
It looks like the derailed 40% hype train is already forgotten 😀

Outside of Chadmont nothing comes close 🤣

Nothingness · Sep 1, 2024

naukkis said:
It's not traditional 24 issue cpu but 6 4-issue cores that can also combined to execute single thread. To do that they need register file interconnect network and complex front end that can split running thread effectively to different cores as there are additional latency when crossing split register file boundaries.

Actually what it is - Amd Bulldozer - AMD didn't implement integer register file interconnect in Bulldozer to being able combine both execution parts to single thread - they probably just failed trying after Keller left. Remember Keller's Alpha 21264 was split register file design with register file interconnnect but without smart front-end needing compiler or programmer effort to extract both cores power in single thread.

There are recent studies in that area. See this for instance: https://inria.hal.science/hal-03740496/document

I guess looking at patents might reveal uses of such schemes (large physical register files are an issue for all advanced CPUs), but I'm not allowed to read patents.

I guess we are getting beyond derailing that thread 😀

SiliconFly · Sep 1, 2024

ondma said:
You may be correct, I dont really know. But if RU is this magic technique, why dont we hear anything about it from AMD? They have plenty of resources to investigate new architectures now.

It's a soft machines patented technology that Intel acquired long back. You can't just copy. Although, they can create derivatives as long as the derivatives don't blatantly infringe on the original patents. Like usual.

SiliconFly · Sep 1, 2024

OriAr said:
Royal Core was real, and the reason it got canned is pretty simple, Intel realized they had no chance whatsoever of hitting its performance targets with it, regardless of the node.
It'd have also meant maintaining 3 different lines of cores as the Coves were still gonna be used on servers.

Nope. Building another new core is a difficult, time consuming & expensive task. But it's a proven technology with 2 iterations of proof of concept CPUs that were powered by RU when Intel acquired it.

jdubs03 · Sep 1, 2024

SiliconFly said:
Nope. Building another new core is a difficult, time consuming & expensive task. But it's a proven technology with 2 iterations of proof of concept CPUs that were powered by RU when Intel acquired it.

That’s one reason why if this is all true, it’s such a disappointment. On the order of 10+ years of work has been spent on this concept. To me I cannot believe that Gelsinger would be so short-sighted and waste all that effort. Particularly since the concept was in such an advanced stage. If they’re not integrating this tech into Nova Lake and its successors, then tbh they deserve to lose further market share to AMD.

SiliconFly · Sep 1, 2024

Doug S said:
See, this is how you know the whole thing was fantasy, or if it ever really existed that it was nothing like this.

No chance in the world that anyone takes a step from the 6/8/10 issue of today all the way to 24. Its completely ridiculous, there is not remotely that much parallelism to extract, you'd execute 24 instructions at once so rarely that the level of complexity could never pay back the huge increase in power consumption.

This is all a bunch of bs, if there ever was a "Royal Core" it sure as hell wasn't this. This is like saying that VW had some secret EV project that would get 1500 mile range out a battery half the cost of today's but still the same size and weight. You might want to believe it, but advancements don't happen like that.

Your assumption is wrong. RU does not need massively wide cores. When conditions are favorable (like idling), it can create a massively wide virtual core by combining regular smaller cores of today. This one is from Ian:

"if each physical core is a 4-wide out-of-order design, if a thread running on a virtual core can utilize the resources of all four cores essentially making a giant 16-wide design".

naukkis said:
It's not traditional 24 issue cpu but 6 4-issue cores that can also combined to execute single thread. To do that they need register file interconnect network and complex front end that can split running thread effectively to different cores as there are additional latency when crossing split register file boundaries.

Actually what it is - Amd Bulldozer - AMD didn't implement integer register file interconnect in Bulldozer to being able combine both execution parts to single thread - they probably just failed trying after Keller left. Remember Keller's Alpha 21264 was split register file design with register file interconnnect but without smart front-end needing compiler or programmer effort to extract both cores power in single thread.

And Intel probably canceled design because it's massive 1T perf with massive power usage. Today such a design is useful only on niche markets.

Exactly. They combine regular cores.

And Intel didn't cancel RU because of any tech issues. It's a proven technology. They cancelled it because of lack of money & Pat is a dimwit.

jdubs03 said:
That’s one reason why if this is all true, it’s such a disappointment. On the order of 10+ years of work has been spent on this concept. To me I cannot believe that Gelsinger would be so short-sighted and waste all that effort. Particularly since the concept was in such an advanced stage. If they’re not integrating this tech into Nova Lake and its successors, then tbh they deserve to lose further market share to AMD.

It appears he's hit the pause button due to severe lack of money. They may resume it once they're in a better position. I don't think it should hurt Nova Lake plans. But anything after that, that uses RU might not get decent upgrades or might get delayed. Also, maybe NVL never had any RU to begin with. Not sure (just guessing), cos a X post recently said, P & E & Royal cores are all *different* cores.

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