Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

jdubs03 · Sep 3, 2024

poke01 said:
I'm just hoping thats the case and a successor comes in 2027. There's a reason why Dell still had LNL in 2026 as an option for the preimum mobile SKU.

They could at least try a refresh for a little performance bump. Otherwise it’ll just get stale.

Their whole segmentation between LNL and PTL is needlessly complicated. I’m not sure why they couldn’t just be consistent with their product segmentation as they scale up the power levels. Hopefully NVL changes that.

DavidC1 · Sep 3, 2024

poke01 said:
https://twitter.com/x/status/1830601888741621890

So Intel you create an amazing x86 SOC with efficiency focused PMIC comparable to M1 but dump it next gen, wtf?

@DavidC1, you were right LNL currently does not have a true successor..

🤦‍♂️

If it looks like a duck and quacks like a duck...

Now my prediction was based on the pessimistic viewpoint that they would have thought Lunarlake was enough to kill WoA advances so they can go back to being lazy and fat.

Except they cannot afford this. They shouldn't can E core Xeon line either. They should address all potential markets. Samsung can at least catch up properly, Intel doesn't even know how to be a fast follower.

Let's hope that's not the case, because if they don't change this mindset, I keep telling you, even if they survive this current debacle, their days are numbered.

Bionic_Squash:

It's ARL-U successor yes.It's got a 4 Xe core IGPU too

Oh you mean the "Arrowlake"-U with Redwood Cove on Intel 3 process? Pantherlake-U is the successor to THAT crap?

Other mega corps had MBA influence their engineering. Intel is basically a finance company with engineering as a side job.

511 · Sep 3, 2024

DavidC1 said:
🤦‍♂️

If it looks like a duck and quacks like a duck...

Now my prediction was based on the pessimistic viewpoint that they would have thought Lunarlake was enough to kill WoA advances so they can go back to being lazy and fat.

I agree they should at least keep most of LNL in design for PTL-U PMIC and On Package Memory and SLC are the highlights of LNL that is akin to M series

DavidC1 said:
Except they cannot afford this. They shouldn't can E core Xeon line either. They should address all potential markets. Samsung can at least catch up properly, Intel doesn't even know how to be a fast follower.

Rouge River Forest is not cancelled according to Bionic Squash and One Raichu so no to this

https://twitter.com/x/status/1822671710015131772

DavidC1 said:
Let's hope that's not the case, because if they don't change this mindset, I keep telling you, even if they survive this current debacle, their days are numbered.

Yeah i agree they need good designs for future

dttprofessor · Sep 3, 2024

PTL is successor of LNL ,all u&h.

DavidC1 · Sep 3, 2024

511 said:
I agree they should at least keep most of LNL in design for PTL-U PMIC and On Package Memory and SLC are the highlights of LNL that is akin to M series

They can't... or to phrase it more accurately, they don't want to, because it would cause them to spend few hundred million $ more they couldn't afford because of why? Terrible choice made to squeeze 0.1% margin and revenue over organically finding new markets.

Lunarlake successor needs a dedicated SoC design.

dttprofessor said:
PTL is successor of LNL ,all u&h.

Don't change, keep being the way you are.

jdubs03 · Sep 3, 2024

Why oh why does ARL-U not use LNC and Skymont? Hopefully PTL-U uses Cougar Cove and Darkmont.

dttprofessor · Sep 3, 2024

DavidC1 said:
They can't... or to phrase it more accurately, they don't want to, because it would cause them to spend few hundred million $ more they couldn't afford because of why? Terrible choice made to squeeze 0.1% margin and revenue over organically finding new markets.

Lunarlake successor needs a dedicated SoC design.

Don't change, keep being the way you are.

MTL 4 Tiles NOC(SOC)/BEOL(intel4) problem
LNL 2 Tiles no problem
PTL 3 Tiles no problem

DavidC1 · Sep 3, 2024

dttprofessor said:
MTL 4 Tiles NOC(SOC)/BEOL(intel4) problem
LNL 2 Tiles no problem
PTL 3 Tiles no problem

Are you from Tomshardware, Techpowerup, or Youtube tech channels by any chance?

Yes I am going to miss this part of Anandtech.

511 · Sep 3, 2024

dttprofessor said:
MTL 4 Tiles NOC(SOC)/BEOL(intel4) problem
LNL 2 Tiles no problem
PTL 3 Tiles no problem

MTL 4 Tiles 3/4 Tiles including the biggest TSMC Intel 4 CPU
LNL 2 Tiles all TSMC
PTL-H 3 Tiles GPU TSMC CPU+NPU+Memory PHY 18A
PTL-U Intel 3 GPU + 18A Compute+NPU+Memory PHY+ N6 IO
not counting filler tiles

DavidC1 · Sep 3, 2024

511 said:
PTL-U Intel 3 GPU + 18A Compute+NPU+Memory PHY+ N6 IO
not counting filler tiles

3 tile approach is a stupid idea for ultra low power chips. ARM vendors don't do this. Monolithic chips still has it's place, because you cannot beat laws of physics, you have to work around it, do your best job with it.

Two tiles on Lunarlake at least made sense, because IO really stopped benefitting from scaling a while ago, and you can get very low leakage dies easier on a mature process.

The GPU is on a separate tile on Pantherlake, which likely a big sacrifice in power terms. The GPU will have to go through another tile to get memory access. Because while Foveros is ok, but is still much slower and higher power than being on-die. How will a GPU over Foveros achieve low power state and have high bandwidth communication with the compute tile, where the memory is?

Latency is a problem in both achieving ultra low real world power and performance. Because if you want low-med active power to be low, you need to turn off clocks and power states in between activities, in the order of milliseconds. If the latency is too high, it simply can't stay in low power state as often.

Did you know that since back in the Pentium III era more than 20 years ago, CPUs were able to reach lower power states in between keystrokes? Latency is absolutely critical for power reasons.

Intel investigated 3D stacked dies publicly as early as the Netburst chips. It never became commercial because 3D stacking active dies immeasurably increases thermal density. So assuming even the IO die to be the interposer has a low chance. Unless they can 3D stack the IO die underneath all the compute dies, they should stick with minimum amount of tiles as possible.

511 · Sep 3, 2024

DavidC1 said:
Two tiles on Lunarlake at least made sense, because IO really stopped benefitting from scaling a while ago, and you can get very low leakage dies easier on a mature process.

The display/codec logic is on the 18A tile so it makes sense to seperate GPU Compute Entirely

DavidC1 said:
The GPU is on a separate tile on Pantherlake, which likely a big sacrifice in power terms. The GPU will have to go through another tile to get memory access. Because while Foveros is ok, but is still much slower and higher power than being on-die. How will a GPU over Foveros achieve low power state and have high bandwidth communication with the compute tile, where the memory is?

Are we assuming Foveros is still on 36 micrometer pitch like MTL cause by panther lake it would have been improved very much

João Bortolace · Sep 3, 2024

511 said:
The display/codec logic is on the 18A tile so it makes sense to seperate GPU Compute Entirely

Are we assuming Foveros is still on 36 micrometer pitch like MTL cause by panther lake it would have been improved very much

Lunar is already using 25um

dttprofessor · Sep 3, 2024

DavidC1 said:
3 tile approach is a stupid idea for ultra low power chips. ARM vendors don't do this. Monolithic chips still has it's place, because you cannot beat laws of physics, you have to work around it, do your best job with it.

Two tiles on Lunarlake at least made sense, because IO really stopped benefitting from scaling a while ago, and you can get very low leakage dies easier on a mature process.

The GPU is on a separate tile on Pantherlake, which likely a big sacrifice in power terms. The GPU will have to go through another tile to get memory access. Because while Foveros is ok, but is still much slower and higher power than being on-die. How will a GPU over Foveros achieve low power state and have high bandwidth communication with the compute tile, where the memory is?

Latency is a problem in both achieving ultra low real world power and performance. Because if you want low-med active power to be low, you need to turn off clocks and power states in between activities, in the order of milliseconds. If the latency is too high, it simply can't stay in low power state as often.

Did you know that since back in the Pentium III era more than 20 years ago, CPUs were able to reach lower power states in between keystrokes? Latency is absolutely critical for power reasons.

Intel investigated 3D stacked dies publicly as early as the Netburst chips. It never became commercial because 3D stacking active dies immeasurably increases thermal density. So assuming even the IO die to be the interposer has a low chance. Unless they can 3D stack the IO die underneath all the compute dies, they should stick with minimum amount of tiles as possib

STX is monolithic ,200+mm^(maybe 230?),4P+8C+NPU+890M, without 4 LPE & system cache, it's too big.

OriAr · Sep 3, 2024

jdubs03 said:
Why oh why does ARL-U not use LNC and Skymont? Hopefully PTL-U uses Cougar Cove and Darkmont.

ARL-U is just MTL-U refresh.
PTL-U isn't a refresh so it'll use Cougar Cove and Darkmont.

Gideon · Sep 3, 2024

igor_kavinski said:
My office PC is faster than that! https://www.intel.com/content/www/us/en/products/compare.html?productIds=75122,75469

Good to know that I'm enjoying better than fighter pilot CPU performance in the comfort of my workplace.

Warning, OT:

Maybe right now (but reality is of course more complicated). Besides they are also receiving upgrades.

The exact details are obviously kept tight under wraps but even just glancing at the upcoming F-35 Tech Refresh 3 hardware (Block 4) It's pretty clear these planes have all kinds of different accelerators on top of (and inside) the "Integrated Core processor" box:

This is also rather cryptic (by design) but I would guess the HW coming online in 2025 (wit the mentioned 37-increase). Even if it was, it probably won't be Haswell soon enough:

Integrated Core Processor

Multi-function processor for processing data for the aircrafts radar, distributed aperture system, electronic warfare, communications, guidance and control, cockpit and helmet displays

37-fold increase in computing power for planned capability upgrades

The ICP system provides enhanced software stability, higher reliability and increased diagnostics resulting in decreased sustainment costs

Panoramic Cockpit Display

Electronic Unit Legacy capabilities increase five-fold with modern multi-core processors

Two independent safety critical display processors for left and right cockpit displays with redundancy

Aircraft Memory System

Delivers twenty times the storage of the legacy system enabling increased sensor data gathering capabilities to expand situational awareness

And considering the small Panoramic Cockpit Display box fits a multi-core processor (a GPU?) I somewhat doubt the large Integrated Core Processor box is onl a single "desktop class" MoBo / CPU. 37x uplift (from Haswell?) also strongly seems to suggest at a server CPU or a multi-CPU design.

There seem to be Separate CNI (communications) and EW racks on top of that.

There's a bit more info aboutthe separate EW rack in the upgrade kit notes:

40Px (former Lot 15) - Technical Refresh 3 (TR-3), Next Generation Distributed Aperture System (Next Gen DAS), Cooling Mod Phase 1 (orifices only), High Efficiency Low Voltage Power Supply (HE-LVPS), Electronic Warfare (EW) Rack 2 Integrated Backplane Architecture (IBA), Radio Frequency Converter (RFC), Electronic Warfare Controller (EWC) Firmware, and Fuel Conduit Mod.
1) ECP-1609 - TR3 - Integrates new Integrated Core Processor (ICP), Panoramic Cockpit Display (PCD), and Aircraft Memory System (AMS) to meet Block 4 processing, memory, and throughput requirements. 2) ECP-1610 - Next Gen DAS - Replaces current DAS due to sensor reliability, while increasing performance to provide larger pixel focal plane array and higher operating temperatures.
-Cooling Upgrade Phase 1 (orifices only) - Increases cooling capacity to support EW growth.
-HE-LVPS - Required for EW mods increased power requirements.
-Rack 2 (IBA), RFC - Replaces legacy EW racks to accommodate modernized EW modules.
3) ECP-1323 - Fuel Conduit Mod - Enable alternate wire routing for Block 4 upgrades for Pre-Lot 15 Aircraft to eliminate the need to route wiring through the dead zone and accommodates future wiring needs.

Oh, and these ICPs also seem to also be duplicated for redundancy (at least one F-35C managed to land in 2012 even with 2of these stopped working)

How? There is a totally separate triple-redundant VMC (Vehicle Management Computer) that keeps the plane airborne even if all the ICPs crash:

So a lot of public domain info on the subject if one knows where to look.

And as proven above f-16.net forum is really good for that kind of info.

TL;DR:
There is more like a server rack worth of different computing devices in 5-th gen fighters, rather than a single CPU / MOBO

igor_kavinski · Sep 3, 2024

Gideon said:
TL;DR:
There is more like a server rack worth of different computing devices in 5-th gen fighters, rather than a single CPU / MOBO

They must be using a realtime OS. Is it QNX or a heavily modified variant? How does one handle multiple cores in realtime? The communication latency needs to be really, really low between the cores to ensure quick response times.

cebri1 · Sep 3, 2024

https://twitter.com/x/status/1830078150664962277

It seems both MSI and Acer will have Lunar Lake based handheld

dullard · Sep 3, 2024

Please ignore this post. I misread a previous one.

As an token for my mistake, here is a link to the Lunar Lake launch livestream in 40 minutes:

Intel Core Ultra Launch Event (Livestream)

See Intel leaders launch the next generation of Intel Core Ultra processors, code-named Lunar Lake.

www.intel.com

igor_kavinski · Sep 3, 2024

cebri1 said:
It seems both MSI and Acer will have Lunar Lake based handheld

Steam Deck better come out with a power optimized Zen 5 or Lunar Lake could destroy its sales!

Or maybe they will decide to give options to consumers. Steam Deck Ryzen Aye Aye edition and Steam Deck Looney Lake edition

Thunder 57 · Sep 3, 2024

I thought today was Lunar Lake day?

dullard · Sep 3, 2024

Thunder 57 said:
I thought today was Lunar Lake day?

35 minutes.

Philste · Sep 3, 2024

Launching Sept. 24th...

511 · Sep 3, 2024

https://videocardz.com/newz/intel-unveils-core-ultra-200v-lunar-lake-series-launching-september-24th

mikk · Sep 3, 2024

Maximum turbo power will be 37W on Lunar Lake. Of course this is a theoretical maximum as always, but it's a lot lower than on MTL-U with up to 57W. This is good.

OriAr · Sep 3, 2024

Intel unveils Core Ultra 200V "Lunar Lake" series, launching September 24th - VideoCardz.com

Intel announces Core Ultra 200V The first product within the new Core series, featuring brand-new CPU and GPU cores. Intel is launching its Core Ultra 200V “Lunar Lake” series today. This is Intel’s first product strictly aimed at the AI PC experience, although they are not yet fully eligible...

videocardz.com

If SPEC 1T numbers are right... Holy ****

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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