It isn't clear from the news coming out of Intel, but my belief is that for a bit there Intel was considering whether to continue fabbing chips at all. That would explain the large capacity buys from TSMC and passing up on delivery of EUV scanners they had previously ordered. When Gelsinger came in he re-committed Intel to fabbing chips, but that required the scale of becoming a real foundry (not the laudhable halfhearted attempt a decade ago) and catching up with TSMC process-wise.
The rumors are / the story is, that after the manufacturing was missing all the deadline, not delivering Bob Swan didn't know what to do, went to TSMC, to put pressure on his own people at Intel
The problem with trying to do five processes in four years when you only have four fabs is that you're going to tie up a lot of that capacity in upgrades and preproduction activities before you're ready for mass production. Those nodes are all short lived - it isn't like there were a lot of products on Intel 4 or will be on Intel 3 and 20A - they are trying to skip through those as quickly as possible but tackling some new "learning" with each one (first EUV, then nanosheet, then BSPDN) That implies a continued need for external capacity until you get back to a more normal process pacing and are able to more effectively utilize your own fab buildings.
Intel has historically operated this way. Most of Intel capacity was on the advanced node, and there was constant upgrading.
This is not efficient, but Intel was never interested in any business with sub 50% gross margins, Intel was never interested in trailing nodes, to utilize them until the wings fall off, selling wafers to outside customers.
Under Gelsinger, Intel set on 2 goals (which are complementary):
1. catch up to leading TSMC node
2. implement the ne nodes for Intel consumption
3. become a foundry to compete with TSMC, bringing TSMC-like efficiency to managing foundry - including keeping trailing edge capacity.
Suppose (using round numbers) accomplishing #1 costs $20 billion and #2 costs $40 and #3 costs $100
It seems like Intel is mortgaging itself to achieve #3, before #1 and #2 are accomplished, which puts the whole enterprise at far greater risk.
Intel could have achieved survival level just reaching #2, without extra $100 billion in debt, but committing itself to foundry (with no customers) could break Intel financially.
That's what I meant by Gelsinger taking high risk rather than low(er) risk approach.
If they can keep their head above water long enough to get a fab or two in Ohio online then assuming they are able to deliver on their process roadmap they'll be fine from a foundry standpoint, and the customers will come simply due to the "made in the USA" (or for non US companies the not "all our eggs in one potential geopolitical hot spot") advantage.
Its just going to take a lot of money to get there - they were really lucky with the timing of the CHIPS act but even then have still needed PE money. If they hadn't borrowed against their overseas cash to drive buybacks/dividends so aggressively they wouldn't have needed the PE guys , but that's what you get when finance people are have too long a leash.
It would be ironic if the allure of the Chips Act and other subsidies lead Intel to imprudent strategy...
Dividends, buybacks, clearly bad use of the money, while TSMC was pouring billions into manufacturing. But that's water under the bridge for current management...