Well 18A is on par with N3P according to TSMC which
N2 is still GAA but not much improvement vs N3P feels like N3B over again
DTCO/STCO will be the next big thing
It is my (admittedly limited) understanding that GAA provides more gate area in the same space. This (in theory) should lead to less leakage and more defined switch states at the transistor level.
If they can get it to work and yield well, I suspect that it will be quite an improvement over N3P. Intel, for most of their history, has had higher density node designs since I have been interested in CPU and process designs (a few decades).
It is pretty much my gut feel that Intel has kept ahead of the industry by its superior process design, not necessarily by its superior processor designs (not to say they are all bad, because some of them have been quite good).
Intel 10nm on par in density to 7nm TSMC. I mean 10nm is bigger. It had better performance due to monolothic die. And Golden Cove whipped Zen 3 on 7nm by 17% better IPC and faster clocks. But more space efficient 10nm was not. And certainly not more power efficient
Well the Zen 5C cores will whip Gracemont e-cores and the only 6% improved Crestmonts. Gracemont e-cores are Skylake level with low 4.X GHz clocks
But Skymont is a massive 37% INT and 68% FP over Crestmont which is already better Gracemont by like 6% and Skymont has Raptor Cove IPC.
SO Skymont will spank Zen 5C easily. Zen 5C is reduced clocks gimped cache and weak Zen 5 IPC which is hardly improvement over Zen 4. And Raptor Cove has better IPC than Zen 4 and 5. And Skymont is supposed to have 2% better IPC than Raptor Cove, It will whip Zen 5C having equal or better clocks in addition to superior IPC.
IIRC, Intel 10nm was more dense than TSMC 7. Please correct me if I am off base here.
I am very much looking forward to benchmark comparisons of Skymont vs ZEN 5c on the same process node. IMO, this will provide the most even comparison of Intel and AMD processor designs ever.
A quick look at the architectures looks like Skymont may be slightly more potent in some respects; however, it lacks SMT that Zen 5c still has. AMD's SMT has also been particularly good adding ~30% performance in highly threaded workloads.
It appears to me that Intel wanted the die space to make the single core performance better. I think we will have to wait for server benchmarks to see if this was a wise decision or not. If Intel can not staunch the server market share bleeding with the next round of server chips, they will indeed be in trouble IMO.
Because government is the penultimate monopoly with near zero consequences to it's actions.
Rather than deregulation things would be better solved if certain crimes couldn't be *cough* bribed *cough* lobbied and/or you can pay your way out of jail and/or you fine the company rather than fining/jailing the individuals responsible.
Volkswagen was fined a massive amount and most of the individuals responsible basically got off with a mere slap in the wrist. Let's say instead they were put in prison regardless of position or fined relative to their earnings, meaning a millionaire would be fined 10x compared to someone having 10x less.
While I agree that prison would definitely be a better deterrent than the company being penalized, You don't tend to stay an executive very long if you are paying out multi-billion dollar fines to CARB every year, so your example is actually a great example of how government oversite has worked.
3nm is not slightly better than 4nm, its a full node advancement.
I would tend to agree; however, the exact impact of a "full node" isn't what it once was for sure. Still, having a 50% larger transistor budget in the same die size target is NOT a small thing. I would argue you would have to be plain brain dead not to produce a more performant CPU design given such an advantage.
So vs N4P, 3%-8% lower power, 1.64x density, -1 to +4% perf. Vs N4X, unknown power savings, unknown density, roughly equal perf? It is unknown whether Zen 5 uses N4P or N4X, and its said that Intel uses N3B, which is not shown here. Im sorry, but this is not enough information to declare with any degree of certainty that density is the only advantage ARL has over Zen 5.
I agree completely. I would definitely say that Zen 5 has ONE advantage that is for certain over ARL ..... it cost less to produce. This is ALSO not "nothing" in the real world.
Zen 5 uses N4P. From the process perspective, N3B’s only significant advantage is logic density.
Still, not insignificant at all with respect to transistor budget IMO.