Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

cebri1 · Monday at 6:58 AM

SiliconFly said:
Intel new code name Razer Lake is out. Maybe a replacement for the now cancelled ARL Refresh. Or a successor to panther lake, with Nova Lake being the desktop. OR follows Nova Lake...

Razer is the successor to Nova.

igor_kavinski · Monday at 7:20 AM

Hitman928 · Monday at 8:03 AM

DrMrLordX said:
Wouldn't N3P (and N3E) require a new set of masks anyway? Plus we only know that Intel has secured an N3B supply from TSMC. Getting N3E or N3P would probably take more cash that Intel probably doesn't have to spend (for now). TSMC is making them pay up front for capacity if I recall correctly.

Not sure what you’re asking. Are you asking if it would require new masks if it started as N3b and was ported?

Nothingness · Monday at 8:41 AM

SiliconFly said:
Intel new code name Razer Lake is out. Maybe a replacement for the now cancelled ARL Refresh. Or a successor to panther lake, with Nova Lake being the desktop. OR follows Nova Lake...

Why does that make me think of that '84 movie Razorback?

Does someone know of a resource that shows Intel CPU codenames and inheritance across generations? This is becoming hilariously messy.

The Hardcard · Monday at 8:45 AM

Doug S said:
Which Intel 10nm? There were how many +'s before they renamed it Intel 7??

Weren’t all of them more dense than N7?

igor_kavinski · Monday at 9:03 AM

Nothingness said:
Does someone know of a resource that shows Intel CPU codenames and inheritance across generations? This is becoming hilariously messy.

List of Intel CPU microarchitectures - Wikipedia

en.wikipedia.org

List of Intel processors - Wikipedia

en.wikipedia.org

Intel Processor Generation Codenames Listed in Order - thinglabs

Intel has given its processor generations different codenames over the years, often inspired by nature or geography. Some well-known codenames

thinglabs.io

Good luck with the inheritance part.

9949asd · Monday at 9:11 AM

511 said:
https://twitter.com/x/status/1838105065586037216
We are so back 47K at 250W 14900K scores 37-38K at 250W

That’s a fake news.

Nothingness · Monday at 9:23 AM

igor_kavinski said:
List of Intel CPU microarchitectures - Wikipedia

en.wikipedia.org

List of Intel processors - Wikipedia

en.wikipedia.org

Intel Processor Generation Codenames Listed in Order - thinglabs

Intel has given its processor generations different codenames over the years, often inspired by nature or geography. Some well-known codenames

thinglabs.io

Good luck with the inheritance part.

These lists are already obsolete, aren't they?

igor_kavinski · Monday at 9:25 AM

Nothingness said:
These lists are already obsolete, aren't they?

No, they seem pretty up to date. One of them mentions Panther Lake.

Nothingness · Monday at 9:39 AM

igor_kavinski said:
No, they seem pretty up to date. One of them mentions Panther Lake.

There's no Razer

igor_kavinski · Monday at 10:04 AM

Nothingness said:
There's no Razer

I think they only update once a codename is mentioned by Intel.

Nothingness · Monday at 10:58 AM

Redwood Cove coverage by C&C: https://chipsandcheese.com/2024/09/22/intels-redwood-cove-baby-steps-are-still-steps/

This includes a nice result about the benefits of SMT.

AcrosTinus · Monday at 11:13 AM

Nothingness said:
Redwood Cove coverage by C&C: https://chipsandcheese.com/2024/09/22/intels-redwood-cove-baby-steps-are-still-steps/

This includes a nice result about the benefits of SMT.

Results of RWC extrapolated from a mobile part.... Isn't the real RWC used in Xeon 6 supposed to be a wider design with lower latency ?

cebri1 · Monday at 11:16 AM

Nothingness said:
Redwood Cove coverage by C&C: https://chipsandcheese.com/2024/09/22/intels-redwood-cove-baby-steps-are-still-steps/

This includes a nice result about the benefits of SMT.

:O

OneEng2 · Monday at 11:42 AM

cebri1 said:
View attachment 108076

:O

Wow.

I had heard, but never seen the benchmarks, people saying that AMD gets more improvement from SMT than Intel does, but this is the first I have seen in it a chart.

I suspect that AMD has devoted a good amount of die space resource to its implementation of SMT in order to achieve such a result. Intel, on the other hand, has a more limited implementation.

This outlines the need for a nuanced discussion when talking about single threaded benchmarks that are used to extrapolate to a multi-threaded workload.

With Intel abandoning SMT completely, separate discussions need to be had on single threaded IPC and multi-threaded IPC.

I am also wondering how the latest bios update AMD released will effect server applications (drastically reduced CCD to CCD latency). There has been some talk in this thread about the relative glue fabric logic used between the 2 companies with some suggesting that Intel's glue logic is better than AMD's infinity fabric design (which I would need to see some benchmarks to either agree or disagree with).

I am very interested to see the LLK testing to see how Intel's design decisions are going to play out.

FlameTail · Monday at 11:59 AM

Intel needs Lunar Lake to succeed to pull the company out of its nosedive

Pull up! Pull up!

www.xda-developers.com

I find headlines like these to be rather disingenuous. Yes, Lunar Lake will repair Intel's reputation and bring them back to the technological edge (with regards to performance-per-watt especially). But Lunar Lake will not help Intel's financials much, because it's a niche part for premium thin-and-light laptops, so rather low volume.

Nothingness · Monday at 12:10 PM

AcrosTinus said:
Results of RWC extrapolated from a mobile part.... Isn't the real RWC used in Xeon 6 supposed to be a wider design with lower latency ?

They don't try to extrapolate anything for the server variant, they analyzed the microarch of Redwood Cove with what they have.

511 · Monday at 1:26 PM

Just found this fake news 🤣

Microsoft Hobbles Intel Once Again

Microsoft’s screwing over Intel in May was just the beginning, things are going downhill fast.

www.semiaccurate.com

igor_kavinski · Monday at 1:35 PM

Nothingness said:
Redwood Cove coverage by C&C: https://chipsandcheese.com/2024/09/22/intels-redwood-cove-baby-steps-are-still-steps/

I'm beginning to think Intel got rid of SMT to avoid the static partitioning of core resources:

Redwood Cove appears to inherit Golden Cove’s 12K entry BTB capacity, but drops latency from 3 to 2 cycles. Strangely, I can only see half the BTB capacity from a single thread. Two threads together can use the entire BTB.

A 128 entry L1 BTB can handle taken branches with just one cycle of latency. An interesting note is it has a maximum throughput of one branch target per cycle as well. If two threads are spamming branches, each thread sustains one taken branch every two cycles. So, the 128 entry L1 BTB doesn’t have more bandwidth than the main 12K entry BTB, just better latency.

Micro-ops from the op cache or decoders are sent to a queue in front of the rename/dispatch stage. Intel increased the size of this queue to 192 entries, up from 144 entries on Golden Cove. If both SMT threads are active, the queue is statically partitioned so that each thread gets half.

And then crazy revelations like this blew my mind:

Intel’s Pentium 4 introduced branch hint extensions. A compiler or assembly programmer can add a prefix indicating whether a branch is more likely to be taken more not taken. The prefixes are as follows:

0x2E: Not-taken hint

0x3E: Taken hint

Subsequent CPUs ignored the hint, likely because increasing transistor budgets allowed better branch predictors, diminishing the value of such static prediction. But Redwood Cove now recognizes the 0x3E taken hint prefix.

All I can think of is, it's so bad that they had to revive something from Pentium 4 !!!

Intel continues to use a 4096 entry micro-op cache. I commented on how I couldn’t see Golden Cove’s full micro-op cache capacity back in 2021. Now I can. Using both SMT threads does the trick. I also dug into performance counters to see if a single thread somehow hit a slowdown unrelated to spilling out of the op cache. Apparently not.

Perhaps Intel decided to permanently partition the micro-op cache between two threads in Golden Cove, unlike prior architectures that could give a thread the entire micro-op cache if the core is in single threaded mode.

Oh great. That's a regression.

Another regression!

the nearly forgotten Broadwell architecture from 2015 brought floating point multiply latency down from 5 cycles in Haswell to 3 cycles. Immediately after, Skylake regressed FP multiply latency back to four cycles. Skylake had 4 cycle latency for FP adds, multiplies, and fused multiply adds. Intel may have reused the fused multiply-add unit with a multiplier of 1 and addend of 0 to implement adds adds and multiplies, respectively. Golden Cove saw Intel cut FP addition latency to 2 cycles. And now Redwood Cove cuts FP multiply latency to 3 cycles.

Wait. Let me see. Skylake. Kaby Lake. Coffee Lake. Coffee Lake Refresh. Comet Lake. Rocket Lake. Alder Lake.

Seven generations they did not have the transistors to bring the FPMUL latency down. No words. Just no words.

alcoholbob · Monday at 1:49 PM

igor_kavinski said:
View attachment 108064

Would be hilarious if Intel sabotaged itself by switching up platforms again after Arrow Lake lmao

igor_kavinski · Monday at 1:52 PM

alcoholbob said:
Would be hilarious if Intel sabotaged itself by switching up platforms again after Arrow Lake lmao

Optimistically, maybe this time it's the other way around. This time whatever comes after the Refresh is progressing so well that they don't need the Refresh to hold them over. Post Nova Lake should be DDR6 so platform change is inevitable but hopefully they will have DDR5 mobos for that too.

poke01 · Monday at 2:26 PM

igor_kavinski said:
Optimistically, maybe this time it's the other way around. This time whatever comes after the Refresh is progressing so well that they don't need the Refresh to hold them over. Post Nova Lake should be DDR6 so platform change is inevitable but hopefully they will have DDR5 mobos for that too.

There is no DDR6 on desktop. It’s LPCAMM2 with LPDDR6

SiliconFly · Monday at 2:32 PM

The Hardcard said:
Weren’t all of them more dense than N7?

Yep.

FlameTail said:
Intel needs Lunar Lake to succeed to pull the company out of its nosedive

Pull up! Pull up!

www.xda-developers.com

I find headlines like these to be rather disingenuous. Yes, Lunar Lake will repair Intel's reputation and bring them back to the technological edge (with regards to performance-per-watt especially). But Lunar Lake will not help Intel's financials much, because it's a niche part for premium thin-and-light laptops, so rather low volume.

With the kinda design wins, LNL doesn't appear to be a low volume part anymore.

poke01 said:
There is no DDR6 on desktop. It’s LPCAMM2 with LPDDR6

Sounds awesome!

Thunder 57 · Monday at 2:47 PM

SiliconFly said:
Yep.

With the kinda design wins, LNL doesn't appear to be a low volume part anymore.

Sounds awesome!

Sounds awful. CPU's prefer latency over bandwidth.

Tom's did a review of the PS5 on a desktop platoform. It wasn't good. For a console it's great. But not as a typical CPU. LPDDR and GDDR suck at latency.

FlameTail · Monday at 3:11 PM

SiliconFly said:
With the kinda design wins, LNL doesn't appear to be a low volume part anymore.

Relatively speaking, it's a low volume part. It will be less volume than ARL.

Also, all those LNL design wins are in the $1000< laptop segment, which is much lower volume than the $1000> laptop segment.

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