Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

Page 821 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

fastandfurious6

Senior member
Jun 1, 2024
214
311
96
Imagine how well a 7800X3D or 9800X3D based gaming laptop would sell.

I know right??? AMD keeps making such bad blunders in mobile SKUs with OEMs etc

whoever is in charge of AMD's deals and relationships with laptop OEMs should be fired 💯💯💯


I don't see much point. Those GPUs in laptops are pretty much always power limited, not CPU performance.

no

perf gains are similar to desktop x3d value, even more valuable in laptops

30-90 extra fps on 1080p

also biggest gains on 1% means never stuttering, huge feature
 
Reactions: darkswordsman17

StefanR5R

Elite Member
Dec 10, 2016
6,057
9,106
136
Dual-CCD cpu's always have possibility that scheluder assigns dependent threads to different cache domains
Linux's task scheduler does not implement a cache-affine thread scheduling policy either. (This is in contrast to its applying a NUMA node affine process scheduling policy by default, which also translates to a NUMA node affine thread scheduling policy.)

- making a them performing worse than just using single CCD.
Not necessarily. If the threads in question don't write and read shared memory a lot, it may turn out better to distribute the threads across cache domains. (Though in these cases, the question is why the programmers chose to parallelize by means of threads rather than by processes.) Because current operating system kernels don't have the profiling data available to be able to tell which cache related scheduling policy is preferable case by case, they aren't applying any.

Userland is nevertheless allowed and capable to constrain scheduling via affinity to logical CPUs. And with AMD server CPUs, operators have the additional possibility to let the BIOS declare each cache domain into a NUMA node. That way, NUMA aware operating system facilities and userland facilities can be coerced into whichever cache domain aware behavior is desired.
 

naukkis

Senior member
Jun 5, 2002
962
829
136
Not necessarily. If the threads in question don't write and read shared memory a lot, it may turn out better to distribute the threads across cache domains. (Though in these cases, the question is why the programmers chose to parallelize by means of threads rather than by processes.) Because current operating system kernels don't have the profiling data available to be able to tell which cache related scheduling policy is preferable case by case, they aren't applying any.

AMD did not use great effort for desktop 2-ccd platform. IO-link is pretty much limiting memory bandwidth already without inter CCD coherency traffic. If program scales past 8-threads and spread to two cache domains with even a little coherency traffic available memory bandwidth starts to suffer too. So AMD did what is only reasonable, disable whole second CCD for programs that can spread itself past 8 thread - like games to prevent unwanted bandwidth starved situations. As CCD's itself have two IO-links AMD should at least made IO-chiplet which uses those both links instead going cheapest possible way. AMD should do proper desktop platform for over 8 cores - or drop out them totally. Now they even have 12-core cpu which is two 6-core domains and is actually downgrade for multithreaded programs from their 8-core cpus.
 

Markfw

Moderator Emeritus, Elite Member
May 16, 2002
26,389
15,513
136

Markfw

Moderator Emeritus, Elite Member
May 16, 2002
26,389
15,513
136
Oh damn, did not expect that. Can you just plop it into any existing genoa system or do you need some kind of prerelease BIOS too? Well, not too much longer until these are out now anyways... Hope you had fun with it 👀
no bios that supports it. No post yet (in a Genoa motherboard)
 
Reactions: Thibsie
Jul 27, 2020
20,917
14,492
146
no bios that supports it. No post yet (in a Genoa motherboard)
I bet you could find a beta BIOS for it on some forum but that would be a bit risky. Or you could open a support ticket and just ask the mobo vendor for the latest beta BIOS without telling them that you want to try Turin. Some support person could inadvertently give you the right BIOS.
 

Markfw

Moderator Emeritus, Elite Member
May 16, 2002
26,389
15,513
136
I bet you could find a beta BIOS for it on some forum but that would be a bit risky. Or you could open a support ticket and just ask the mobo vendor for the latest beta BIOS without telling them that you want to try Turin. Some support person could inadvertently give you the right BIOS.
I won't use a non-mfg bios. I already asked supermicro, and their answer was "nothing until it is released". So dead until Oct 10th (most likely)
 
Mar 11, 2004
23,341
5,772
146
Strix Halo is going to be more optimized, and it would be ideal to have 1 CCD version with V-Cache.

Strix Halo should have had X3D as part of its design intent. But AMD is not a consumer focused company, so expect perpetual disappointment (its not just them, careful what ya wish for, we'll be looking at ARM and low power/low core count/etc chips). But what if...

Strix Point is a flop only worth upgrade from 4800/5800h, not from phoenix

AyyyyyyyyyyyyyyyyyyyEyyyyyyyyyyyyyyyyyyyyyyyye

This isn't new, this is the case for all computing markets (see iPhone 16 Pro). Tech enthusiasts really need to start looking for new hobbies as tech just is not going to be exciting for most. The big breakthroughs are all gonna be enterprise stuff or usability (aka, making headsets worthwhile to wear, improving interface - honestly I think there's more excitement about mechanical keyboards than there are about processors these days).
 
Jul 27, 2020
20,917
14,492
146
Last edited:

StefanR5R

Elite Member
Dec 10, 2016
6,057
9,106
136
For context, here are entries with EPYC 9654P (Zen 4 96c):
https://ranker.sisoftware.co.uk/sho...d4ecdae2d7e2d3f587ba8aacc9ac91a187f4c9f9&l=en

That CPU is on an unreleased updated version of this mobo model: https://eps.msi.com/en/product/server-motherboards/D3051-D3051GB4N-10G

The newer one is D4051 while older one is D3051.
Going from AM5 to SP5 is quite an update indeed. ;-)
 
Reactions: igor_kavinski
sale-70-410-exam    | Exam-200-125-pdf    | we-sale-70-410-exam    | hot-sale-70-410-exam    | Latest-exam-700-603-Dumps    | Dumps-98-363-exams-date    | Certs-200-125-date    | Dumps-300-075-exams-date    | hot-sale-book-C8010-726-book    | Hot-Sale-200-310-Exam    | Exam-Description-200-310-dumps?    | hot-sale-book-200-125-book    | Latest-Updated-300-209-Exam    | Dumps-210-260-exams-date    | Download-200-125-Exam-PDF    | Exam-Description-300-101-dumps    | Certs-300-101-date    | Hot-Sale-300-075-Exam    | Latest-exam-200-125-Dumps    | Exam-Description-200-125-dumps    | Latest-Updated-300-075-Exam    | hot-sale-book-210-260-book    | Dumps-200-901-exams-date    | Certs-200-901-date    | Latest-exam-1Z0-062-Dumps    | Hot-Sale-1Z0-062-Exam    | Certs-CSSLP-date    | 100%-Pass-70-383-Exams    | Latest-JN0-360-real-exam-questions    | 100%-Pass-4A0-100-Real-Exam-Questions    | Dumps-300-135-exams-date    | Passed-200-105-Tech-Exams    | Latest-Updated-200-310-Exam    | Download-300-070-Exam-PDF    | Hot-Sale-JN0-360-Exam    | 100%-Pass-JN0-360-Exams    | 100%-Pass-JN0-360-Real-Exam-Questions    | Dumps-JN0-360-exams-date    | Exam-Description-1Z0-876-dumps    | Latest-exam-1Z0-876-Dumps    | Dumps-HPE0-Y53-exams-date    | 2017-Latest-HPE0-Y53-Exam    | 100%-Pass-HPE0-Y53-Real-Exam-Questions    | Pass-4A0-100-Exam    | Latest-4A0-100-Questions    | Dumps-98-365-exams-date    | 2017-Latest-98-365-Exam    | 100%-Pass-VCS-254-Exams    | 2017-Latest-VCS-273-Exam    | Dumps-200-355-exams-date    | 2017-Latest-300-320-Exam    | Pass-300-101-Exam    | 100%-Pass-300-115-Exams    |
http://www.portvapes.co.uk/    | http://www.portvapes.co.uk/    |