There are certainly several limits which each are more or less costly to bump up (but which may or may not have been reached by the 96 MB 16-way associative config yet). For example, my understanding is that L3$ tags need to be tracked in the IOD, which imposes whatever limit of cache line count they thought of back in the day when they designed this IOD. (Somebody correct me if I got this wrong.)
Edit, or on the hardware side, a 32 + 64 + 64 stack might have worse timings and/or thermals than the 32 + 64 stack, possibly negating whatever diminishing returns would come from 160 MB L3$ compared to 96 MB.
Most tech products do not improve that much gen-on-gen to be worth upgrading to nowadays, that's just a consequence of CPUs being a mature thing at this point.phoenix -> stx is really not worth the upgrade
phoenix -> stx is really not worth the upgrade
I also did 5800H -> phoenix and it also wasn't really worth it tbh, main benefit is lower thermals
phoenix -> halo/firerange will be worth it
But that doesn't mean Strix is a flop.phoenix -> stx is really not worth the upgrade
I also did 5800H -> phoenix and it also wasn't really worth it tbh, main benefit is lower thermals
1T perf won't be much better than what Strix has, so It leaves only nT.phoenix -> halo/firerange will be worth it
I'm not saying it's impossible. I'm saying it doesn't make sense for them to increase V$ on the 9800X3D and not on the entire range. I believe if they have a a new 96MB V$ design, every SKU will have it. Not just the 9800X3D.Even AMD hasn't decided it yet. They had tested various option in lab and successful, like dual layer Vcache and dual CCD Vcache, but nonetheless would increase the cost.
That source is so questionable I would not believe this for 1 second.
It says "64MB + 128MB Vcache" for the 9950X + 9900X
then it says "32MB + 96MB VCache" for the 9800X
They can't even get the fine details correct.
what if it's true? bet
If guys want to spread a rumor, they want to do it fast. Can't triple-check for typos then.i think it's more of a mistake due to fabricating the info.
A question: Do the lower end Epycs (16C/32T) have eight CCDs with just two active cores per CCD? Where do I find such information?
A question: Do the lower end Epycs (16C/32T) have eight CCDs with just two active cores per CCD? Where do I find such information?
That was the actual reason for my question. How is that cache arranged? Is that 384MB per two CCDs? Or is that 96MB for each of eight CCDs?also 9184X is 16 core with 768MB L3 Cache
that's insane
how does it perform? cant find benchmarks
That was the actual reason for my question. How is that cache arranged? Is that 384MB per two CCDs? Or is that 96MB for each of eight CCDs?
The number of people not understanding how AMDs Chiplet CPUs work is amazing. V-Cache on both CCDs will bring exactly 0 gaming uplift. It only makes MT slower if they didn't completely fix clock Issues.v-cache in more CCDs = immense gains
(not only in games)
is 96mb per CCD really a hard limit? why would it be?
what is the limiter and why couldn't they change it for a new SKU?
The number of people not understanding how AMDs Chiplet CPUs work is amazing. V-Cache on both CCDs will bring exactly 0 gaming uplift. It only makes MT slower if they didn't completely fix clock Issues.
That was the actual reason for my question. How is that cache arranged? Is that 384MB per two CCDs? Or is that 96MB for each of eight CCDs?
For games, a 16 Core Ryzen is 2 8 cores with 32MB L3 each. So a 9950X3D with V-Cache on both CCDs will look like 2 9800X3D for games. There's 0 extra performance, the only difference is that it isn't possible for a game to Land on a CCD without extra Cache.doubt
Shouldn't that statement include the caveat that for games able to fully utilise more than 8C cores, also having the cache on the second CCDs should offer somewhat more than 0 extra performance?For games, a 16 Core Ryzen is 2 8 cores with 32MB L3 each. So a 9950X3D with V-Cache on both CCDs will look like 2 9800X3D for games. There's 0 extra performance, the only difference is that it isn't possible for a game to Land on a CCD without extra Cache.
Great but dude, you just tempting game companies to take away the X3D supply from us poor little people!How would dual cache 9950X3D be for game servers?
Functional yields should be pretty high on Zen 5 CCDs since it's just over 70mm² and TSMC's yields for 4nm should be pretty good.can someone confirm most CPU SKU market segmentation is due to yields right?
same core, just weaker yields get disabled cores and sold cheaper