Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

511 · Oct 2, 2024

Let me correct
On October 7 we will get official slides leaked like Lunar lake
On October 10 the official launch will begin

naukkis · Oct 2, 2024

Doug S said:
Once you've lost your mind and think a 24 wide design isn't the stupidest thing ever, you better figure out a way to keep it doing something halfway useful when the magic compiler you're depending on fails to materialize (like they always do)

It wasn't traditional 24-way cpu but 4 clustered 6-way cpus with register-to.register moves and ability to execute single thread together. X86 is worst ISA to do such a cpu so Intel would have need to implement new ISA to support that cpu. I speculate that Jim Keller did want to do it with Risc-v ISA and after Intel changed that to x86( and doomed it to fail) he left. Actually rest of Royal core lead designers also left Intel and are building that Royal Core on Risc-V under new startup Ahead computing - curiously see if they can bring something out.

And if they get something good out Intel sure need to reorganize their management layer - sack everybody.

Wolverine2349 · Oct 2, 2024

511 said:
The sample you have is it a QS?

So Arrow Lake can do DDR5 Gear 1??

Shoudl that more than make up for the IMC being on a spearate tile form CPU corers and ring unlike Raptor and Alder? Raptor and Alder can only do DDR5 Gear 2, but they have faster IMC latency due to the IMC being on the same die on CPU cores and ring? Am I right on that thinking?

9949asd · Oct 2, 2024

Wolverine2349 said:
So Arrow Lake can do DDR5 Gear 1??

Shoudl that more than make up for the IMC being on a spearate tile form CPU corers and ring unlike Raptor and Alder? Raptor and Alder can only do DDR5 Gear 2, but they have faster IMC latency due to the IMC being on the same die on CPU cores and ring? Am I right on that thinking?

I don’t know it’s a bug or not. For the cudimm When showing 1:1 is g2, when showing 1:2 is g4.
For ARL there is no d4 inc anymore.

Magio · Oct 2, 2024

gdansk said:
Hmm? I thought it was more dense.

If you read between the lines of Intel's own communication, this isn't a big surprise:

This is Intel's own assessment of how their nodes will fare against TSMC's, which logically you'd assume would have Intel pit 18A against TSMC's top of the line node when 18A is set for HVM.

"≈" in a marketing slide may as well mean "slightly worse", and 18A will reach HVM before N2 so TSMC's top of the line would be N3P at that point. So 18A having slightly worse density than N3P is the logical take away from this. But keep in mind N2 is "only" expected to have +/- 15% density uplift over N3E, so that's not actually too bad especially as 18A-P would bridge some of that gap again probably within reasonable timelines.

"+≈" on the other hand in marketing speech would most likely mean "maybe barely better but generally as good", so they expect 18A to fare well in PPW (at least in HPC scenarios) vs N3E/P and 14A to finally actually see them reclaim the density lead even if not by much.

Napkin math from SemiAnalysis' prediction that 18A will have a 50+% density uplift over Intel 3 would probably mean it should land a bit above 200MTr/mm² which is indeed a tad behind N3E/P.

KompuKare · Oct 2, 2024

coercitiv said:
On the 10th we'll have a good idea about productivity performance, and then 2 weeks of arguing about gaming performance will follow.

If gaming performance is very influenced by memory speeds above spec then those arguments may last a lot longer than 2 weeks!

CouncilorIrissa · Oct 2, 2024

LNL die shots.

https://twitter.com/x/status/1841497643178148185

GTracing · Oct 2, 2024

CouncilorIrissa said:
LNL die shots.

https://twitter.com/x/status/1841497643178148185

I measure the four P cores at 1632791 pixels with L3 cache and 1179648 pixels without L3. The four E cores are 441548 pixels. That makes the E cores 27% the size of the P cores with L3, or 37% the size of P cores without the L3. Good to see the increase in performance didn't balloon the E core's area.

mvprod123 · Oct 2, 2024

9949asd · Oct 2, 2024

Geekwan lunar lake test
Limited board power to 30w and 15w, lunar lake crush every things.

9949asd · Oct 2, 2024

511 · Oct 2, 2024

Lunar lake is really good except the mod MT perf at higher Power it's really a good chip and Snapdragon hype has been dead 🤣

Abwx · Oct 2, 2024

9949asd said:
Geekwan lunar lake test
Limited board power to 30w and 15w, lunar lake crush every things.
View attachment 108556 View attachment 108557 View attachment 108559 View attachment 108561 View attachment 108562

First pics : 258V 22W soc power, HX370 15W.

Last pic : 258V 12W soc power, HX370 9W.

So that s just a tiny 50% more power.

Yeah, it crush everything when it comes to cheating.

9949asd said:
View attachment 108565

Same here, 258V at 12W vs 9W for the 370, that s just a joke of a test.

controlflow · Oct 2, 2024

Abwx said:
First pics : 258V 22W soc power, HX370 15W.

Last pic : 258V 12W soc power, HX370 9W.

So that s just a tiny 50% more power.

Yeah, it crush everything when it comes to cheating.

Same here, 258V at 12W vs 9W for the 370, that s just a joke of a test.

You clearly did not watch the video.

DavidC1 · Oct 2, 2024

Magio said:
Napkin math from SemiAnalysis' prediction that 18A will have a 50+% density uplift over Intel 3 would probably mean it should land a bit above 200MTr/mm² which is indeed a tad behind N3E/P.

And they are completely wrong, ignoring Intel's own presentation that 18A offers mere 30% density improvement over Intel 3.

controlflow said:
You clearly did not watch the video.

What else can you expect from him?

mvprod123 · Oct 2, 2024

It's still worse in terms of power efficiency than the M1, which is 4 years old and made on a TSMC N5 node. It's amusing

Abwx · Oct 2, 2024

controlflow said:
You clearly did not watch the video.

Power is stated on the captured screens, and yet he write that it s at 15W despite 22W
being displayed on the screen shots.

cannedlake240 · Oct 2, 2024

DavidC1 said:
And they are completely wrong, ignoring Intel's own presentation that 18A offers mere 30% density improvement over Intel 3.

TSMC N3 is also a mere 30% density increase over N5. Because it's chip density not logic density. Chips aren't made entirely out of highest density logic cells

SiliconFly · Oct 2, 2024

GTracing said:
I measure the four P cores at 1632791 pixels with L3 cache and 1179648 pixels without L3. The four E cores are 441548 pixels. That makes the E cores 27% the size of the P cores with L3, or 37% the size of P cores without the L3. Good to see the increase in performance didn't balloon the E core's area.

P core to E core ration is roughly 1:3. Also, if not for the massive NPU, we could've almost had 8 more E cores.

adroc_thurston · Oct 2, 2024

cannedlake240 said:
TSMC N3 is also a mere 30% density increase over N5

This doesn't have BSPDN or any other (new) scaling boosters.

511 · Oct 2, 2024

DavidC1 said:
And they are completely wrong, ignoring Intel's own presentation that 18A offers mere 30% density improvement over Intel 3.

Intel said Chip density they never said logic density two are different things
Chip density means Logic+Sram+Aanalog
Analog doesn't scale well Sram scaling is nearly dead for now

DavidC1 said:
What else can you expect from him?

Yeah he is here to 🧌 don't mind him

511 · Oct 2, 2024

adroc_thurston said:
This doesn't have BSPDN or any other (new) scaling boosters.

BSPDN has routing benefits and Droop benifits you can read Intel 4 + Power via

adroc_thurston · Oct 2, 2024

511 said:
BSPDN has routing benefits and Droop benifits you can read Intel 4 + Power via

It has net density benefits. It's a scaling booster like many others.

Det0x · Oct 2, 2024

New coolers recommned for Arrow Lake

https://videocardz.com/newz/intel-core-ultra-200-lga-1851-cpu-hot-spot-reportedly-a-bit-further-north-than-lga-1700s

DavidC1 · Oct 2, 2024

cannedlake240 said:
TSMC N3 is also a mere 30% density increase over N5. Because it's chip density not logic density. Chips aren't made entirely out of highest density logic cells

Please take a look at Lunarlake and tell me there's enough SRAM cells to change density improvements from 60% to 30% just because SRAM doesn't scale as well. Even if we assume SRAM improvement is 0%, it's a big stretch.

Daniel Nenni was guessing and he's wrong.

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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