Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Page 544 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

Tigerick

Senior member
Apr 1, 2022
702
632
106






As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E012 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4TSMC N3BTSMC N3BIntel 18A
DateQ4 2023Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P8P + 16E4P + 4E4P + 8E
LLC24 MB36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15



Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



 

Attachments

  • PantherLake.png
    283.5 KB · Views: 24,014
  • LNL.png
    881.8 KB · Views: 25,501
Last edited:

H433x0n

Golden Member
Mar 15, 2023
1,222
1,600
96
That s wrong, for the S16 Computerbase measured 28W in CB in HVinfo and NBC measured a little more than 30W for CB at the main, so AMD s telemetry is very accurate and it so for many years, beside you re talking of the Z1ex, dunno what it has to do with the 370.

All numbers for 288V and 370 can be found here :

Where does it say they are measuring power draw in a similar fashion as Geekerwan? I read the translated text and I do not see it.
 

SiliconFly

Golden Member
Mar 10, 2023
1,651
996
96
Yes for sure. Sick and tired of NPUs and this AI garbage hype.
These NPUs are mostly just for marketing purposes I think. I assuming most of the AI apps can use the GPU instead. A bit inefficient maybe, but who cares.

The 3:1 ratio for P vs E still applies. More embarassment for P core team.
P core team is a lost cause. Hope they come up with something good sooner.

LNL is simply on a different level in real world low power applications compared to the AMD solutions.
LNL looks real awesome. I don't understand why these idiots have to stop with just one iteration.

But despite this, you can see that LionCove is a completely new project from scratch.
Are you sure it's a new design? I'm under the impression, LNC is basically a port of RWC from in-house design tools to industry standard design tools while being modular & agnostic (portable). Meaning, it's basically RWC with some decent core upgrades but on a solid foundation that'll help them immensely going forward. Am I correct? If yes, I'm expecting some decent uplift starting cougar cove itself.

Oh that's Very Bad for an N3 core.
Since it a N3B core, it's kinda easier to compare with M3 which is also N3B. Can someone figure out whats the size of a M3 P core with L2. That'll be true apples-to-apples comparison. Something we've all been waiting for.

Can x86 cores at least catch up to M3 what is this
A M3 P core vs LNL P core direct comparison should shed more light on area-efficiency, overall-efficiency, performance (per transistor or area or whatever the unit is), etc. It's gonna be very interesting. Will show how behind Intel P core team is.

They go nowhere, this review is just dubbious.
Naturally. It's gotta be dubious.

Zen 6 40% and Nova Lake 40% Cope ?
Nove Lake only 40% ST? ;-)

Oh the fanboy wants to compare multicore performance now? Tell me, a 4+4 8c8t compare to 4+8 12c24t, and you proud of it?
Iirc, one of the mod wasn't happy when the term fanboy was used. I guess it's on this forums blacklist or something. It's never too late to make an edit.

This is IPC, i.e. comparison at the same clock speed.

The x86 design cores from Intel and AMD provide high clock speeds, which on the one hand simplifies the design, but also makes the core logic less dense than it could be. High clock speeds mean many compromises in the core microarchitecture.

Apple designs cores for much lower clock speeds, so it can have a pipeline with fewer stages, lower cache latencies, and greater capacity. Apple cores are the power of huge amounts of resources: L1-I 192KB, L1-D 128KB, 10-Wide decoding, ROB 900+ 8xALU and very low latency.

That's it in a nutshell and simplified way.
But I think it also makes the Apple P cores a bit fat.

And Intel/AMD needs to follow that direction, because I suspect large L1 caches are also contributing to efficiency in their designs because it keeps lot of data from going out into slower, higher power cache levels and memory.

The basis of Apple's design is also having stellar design team, because being able to have 4GHz clocks at such low power at just 9 pipeline stages and humongous L1 cache with 3 cycle latency is amazing. The E core team can still do quite a bit better, which is catch up with Apple's. It is even more impressive when you consider Mx chips have been stagnating for a while with smart engineers all into "AIeeee" hype and moving to startups.
I remember reading most of the top talent in the Apple silicon team have left leaving the rest to just iterate. Probably one of the reasons M series silicon hasn't had any major performance/efficiency jumps lately.

If you can't control yourself than I have to suggest you have a bit of problem yourself. You can feel uncomfortable about something but still be more civil.

As they say, if you want to stay, you gotta "play the game".
True.

Excuse me? Am I in a AMD thread ?
Self restraint is crucial. The mods aren't too kind. If @awbx continuously tries to flamebait, the best option is to report those posts. He knows the rules & plays by them, so should the rest of us.

Core architecture is the key that matters most (IPC). Intel claims that future generations will no longer focus on high clock speeds, but on IPC. It will be interesting to see where this goes.
Panther Cove?
 

Abwx

Lifer
Apr 2, 2011
11,612
4,469
136
Where does it say they are measuring power draw in a similar fashion as Geekerwan? I read the translated text and I do not see it.

Go at NBC they have scores of power measurements at the main, i linked an article,
difference is that i read all articles be it about AMD or Intel while here there s apparenly lot of people who only rely on earsay when it comes to AMD, hence the lengthy and useless debate because there s homewoks that are not done.
 

511

Golden Member
Jul 12, 2024
1,038
897
106
Therefore history doesn't repeat but rhymes. It is mini Netburst to Core all over again. Raptorlake degradation is Pentium III 1.13GHz but 23 years later. The motivation is quite similar. Both pushed clocks too high to better go against competition, which in both cases is AMD.
It was not really the clocks but a combination of different things all happening at once
>eTVB
>MOBO maker defaults
>Core requesting Insane VIDs
> Bug in clock circuitry
But ut will hamper future sale at least Intel 7 is a depreciated Node so everything now only cost them the amount to make it they can literally sell i9 for $250-300 and make a profit
 
Reactions: Thibsie

SiliconFly

Golden Member
Mar 10, 2023
1,651
996
96
Where does it say they are measuring power draw in a similar fashion as Geekerwan? I read the translated text and I do not see it.
Arguing with him is an exercise in futility. You can't see it because of the "homewoks that are not done". Generally speaking, some can't handle the fact Lunar Lake is far more efficient than their favorite cpu. Which reminds me of this...

 
Last edited:

AMDK11

Senior member
Jul 15, 2019
438
360
136
Are you sure it's a new design? I'm under the impression, LNC is basically a port of RWC from in-house design tools to industry standard design tools while being modular & agnostic (portable). Meaning, it's basically RWC with some decent core upgrades but on a solid foundation that'll help them immensely going forward. Am I correct? If yes, I'm expecting some decent uplift starting cougar cove itself.
LionCove is a fundamentally new project and has little in common with RedwoodCove. The change from the unified FP-ALU schedule and the separation of FP into a separate block and ALU into a separate one makes this a fundamental change. I believe that LionCove is the beginning of major changes in P-Core. Time will verify whether I was right.
 
Reactions: Henry swagger

Jan Olšan

Senior member
Jan 12, 2017
427
776
136
It was not really the clocks but a combination of different things all happening at once
>eTVB
>MOBO maker defaults
Pretty sure those were defaults that the motherboard makers used more or less under Intel's influence, because Intel was who benefited.
After all, you only have to look at AM4 and AM5 where specs are specs and this thing doesn't exist. And also, remember how quickly Intel cracked down on overclocking of non-K CPUs.
Intel always had the power to stop this instantly but they didn't, which clearly shows the "4095W" way was how Intel wanted it.
>Core requesting Insane VIDs
> Bug in clock circuitry
No! The clock tree was simply the first of the circuits that would fail/show damage from the generally dangerous voltage. That is not a bug and you can't really blame the poor transistors from dying due to mistakes being made elsewhere.

But ut will hamper future sale at least Intel 7 is a depreciated Node so everything now only cost them the amount to make it they can literally sell i9 for $250-300 and make a profit
 

Hitman928

Diamond Member
Apr 15, 2012
6,391
11,392
136
By the way, here's the core area numbers on Lunarlake.

Skymont: 1.15mm2, 1.75mm2 with L2
Lion Cove: 3.43mm2 without L2, 4.67mm2 with

@Hitman928 The above is fair bit smaller than the block diagram based shot they gave a while ago. Skymont was 1.3mm2 based on the block diagram shot.

The 3:1 ratio for P vs E still applies. More embarassment for P core team.

I’m on vacation right now but will take a look when I get back.
 

511

Golden Member
Jul 12, 2024
1,038
897
106
Pretty sure those were defaults that the motherboard makers used more or less under Intel's influence, because Intel was who benefited.
After all, you only have to look at AM4 and AM5 where specs are specs and this thing doesn't exist. And also, remember how quickly Intel cracked down on overclocking of non-K CPUs.
Intel always had the power to stop this instantly but they didn't, which clearly shows the "4095W" way was how Intel wanted it.
Oh yeah i agree they should have Stopped the nonsense it Lives on Laptops as well look at MTL/RPL-H with 115W that's nonsense 80W should be the max really
No! The clock tree was simply the first of the circuits that would fail/show damage from the generally dangerous voltage. That is not a bug and you can't really blame the poor transistors from dying due to mistakes being made elsewhere.
I don't know exactly what it means tbh but it is a Design flaw nonetheless do we not call it a bug ?
 

9949asd

Member
Jul 12, 2024
139
96
61
Pretty sure those were defaults that the motherboard makers used more or less under Intel's influence, because Intel was who benefited.
After all, you only have to look at AM4 and AM5 where specs are specs and this thing doesn't exist. And also, remember how quickly Intel cracked down on overclocking of non-K CPUs.
Intel always had the power to stop this instantly but they didn't, which clearly shows the "4095W" way was how Intel wanted it.

No! The clock tree was simply the first of the circuits that would fail/show damage from the generally dangerous voltage. That is not a bug and you can't really blame the poor transistors from dying due to mistakes being made elsewhere.

Pretty sure those were defaults that the motherboard makers used more or less under Intel's influence, because Intel was who benefited.
After all, you only have to look at AM4 and AM5 where specs are specs and this thing doesn't exist. And also, remember how quickly Intel cracked down on overclocking of non-K CPUs.
Intel always had the power to stop this instantly but they didn't, which clearly shows the "4095W" way was how Intel wanted it.

No! The clock tree was simply the first of the circuits that would fail/show damage from the generally dangerous voltage. That is not a bug and you can't really blame the poor transistors from dying due to mistakes being made elsewhere.
It’s mother board company who want to show the difference performance on their MB, then come out with “default “ enabled 4096w 512A limit. This happened like almost 10years, but intel didn’t stop it.
Good news is z890 b860 will force to use intel default setting when out of box.
 

511

Golden Member
Jul 12, 2024
1,038
897
106

Doug S

Platinum Member
Feb 8, 2020
2,888
4,912
136
Reactions: OneEng2

cannedlake240

Senior member
Jul 4, 2024
207
111
76
LionCove is a fundamentally new project and has little in common with RedwoodCove. The change from the unified FP-ALU schedule and the separation of FP into a separate block and ALU into a separate one makes this a fundamental change. I believe that LionCove is the beginning of major changes in P-Core. Time will verify whether I was right.
Nah, this is a misconception likely originating from MLID, about Lioncove bring a part of royal core/an entirely new project and uarch team led by Jim Keller. That's simply not true. Lioncove still has a lot in common with redwood cove and all prior Intel core uarch as shown by C&C and David Huang's articles. The core still behaves largely the same in a lot of key metrics
 
Reactions: Tlh97 and DavidC1

mvprod123

Member
Jun 22, 2024
186
198
76
I remember reading most of the top talent in the Apple silicon team have left leaving the rest to just iterate. Probably one of the reasons M series silicon hasn't had any major performance/efficiency jumps lately.
The results of the Oryon core showed that the role of people who left Apple was exaggerated, Apple did not lose its leadership in IPC during these 4 years.

A M3 P core vs LNL P core direct comparison should shed more light on area-efficiency, overall-efficiency, performance (per transistor or area or whatever the unit is), etc. It's gonna be very interesting. Will show how behind Intel P core team is.
I couldn't find the size of the M3 P-core, but instead found the size of the M2 P-core. The Lunar Lake P-core roughly matches the performance of the M2 P-core.


 
Reactions: SiliconFly

Jan Olšan

Senior member
Jan 12, 2017
427
776
136
Oh yeah i agree they should have Stopped the nonsense it Lives on Laptops as well look at MTL/RPL-H with 115W that's nonsense 80W should be the max really

I don't know exactly what it means tbh but it is a Design flaw nonetheless do we not call it a bug ?
Let me rephrase it: inevitably, something will break in the processor if you feed it excessive voltage. It just happened to be the clock tree. It's likely that the next-in-the-line to failing circuitry doesn't have much better voltage tolerance. Clock tree is also a permanently stressed element, so it gets voltage-fried more often than some other parts.

It's quite possible it was carried over from Alder Lake. You could say it was flawed if it was supposed to only get damaged at 1.6V and it already gave up 1.55V, but I expect it wasn't really like that, the circuitry likely just got more voltage than it was designed to safely handle (blame: the whole voltage control system).

It’s mother board company who want to show the difference performance on their MB, then come out with “default “ enabled 4096w 512A limit. This happened like almost 10years, but intel didn’t stop it.
Good news is z890 b860 will force to use intel default setting when out of box.
How can motherboard vendors show a difference when all of them do this? They just ended up being on square one again, so I don't see this as being true.
You could say that it allows them to show a difference between their own lowly H610 board and another pricy Z790 board. But in that case, why didn't they ask AMD to get them similar ability on AM4 and AM5 platform?
 

H433x0n

Golden Member
Mar 15, 2023
1,222
1,600
96
Go at NBC they have scores of power measurements at the main, i linked an article,
difference is that i read all articles be it about AMD or Intel while here there s apparenly lot of people who only rely on earsay when it comes to AMD, hence the lengthy and useless debate because there s homewoks that are not done.

I’ll just ask it outright, do you believe it’s possible that Lunar Lake could be a better low power SoC than Strix?

I’m getting the sense that the only results you will consider valid are the ones that would show Strix as being more efficient.
 
Reactions: SiliconFly

9949asd

Member
Jul 12, 2024
139
96
61
Let me rephrase it: inevitably, something will break in the processor if you feed it excessive voltage. It just happened to be the clock tree. It's likely that the next-in-the-line to failing circuitry doesn't have much better voltage tolerance. Clock tree is also a permanently stressed element, so it gets voltage-fried more often than some other parts.

It's quite possible it was carried over from Alder Lake. You could say it was flawed if it was supposed to only get damaged at 1.6V and it already gave up 1.55V, but I expect it wasn't really like that, the circuitry likely just got more voltage than it was designed to safely handle (blame: the whole voltage control system).


How can motherboard vendors show a difference when all of them do this? They just ended up being on square one again, so I don't see this as being true.
You could say that it allows them to show a difference between their own lowly H610 board and another pricy Z790 board. But in that case, why didn't they ask AMD to get them similar ability on AM4 and AM5 platform?
Because after the first one does it, everyone must follow up. Unlock the power limit happened at 4770k to 4790k. Unlock power limit can boost up 5 to 10% performance.

About amd motherboard, they did it too. Remember when 7800x3d 7950x3d just came out there were some cpu burned? Venders was overvoltages it, but amd quickly force them to change bios.
 

poke01

Platinum Member
Mar 8, 2022
2,581
3,409
106
I’ll just ask it outright, do you believe it’s possible that Lunar Lake could be a better low power SoC than Strix?

I’m getting the sense that the only results you will consider valid are the ones that would show Strix as being more efficient.
It’s impossible for Strix point to be lower power than Lunar lake, even next gen Zen6 APU won’t reach Lunar levels if AMD doesn’t follow the design of Lunar.
 

poke01

Platinum Member
Mar 8, 2022
2,581
3,409
106
There are other hacks to get lower power.
But they're also $$$.
PTL and NVL mobile both focus on trimming down the excess in the name of more palatable BOM, and for a good reason.
Now NVL might have a chance? Isn’t that Arctic Wolf for e core. Something tells me that core might be cool
 

DavidC1

Golden Member
Dec 29, 2023
1,211
1,932
96
I’m on vacation right now but will take a look when I get back.
I looked at the block diagram shot again. I had suspicions that it wouldn't be 100% accurate because it wasn't an actual die shot.

With the block diagram shot I'm getting 1.3-1.35mm and 4.4mm for P and E, w/o L2 on E and w/L2 on P. It isn't the P core size that got smaller, the E core did though. The actual die shot I'm getting 1.14-1.15mm2 w/o L2 and 1.75mm2 with L2.
 
Last edited:

H433x0n

Golden Member
Mar 15, 2023
1,222
1,600
96
There are other hacks to get lower power.
But they're also $$$.
PTL and NVL mobile both focus on trimming down the excess in the name of more palatable BOM, and for a good reason.
Eh, the costs are worth it and required to compete at the highest level.

I think it’d be in best interest of Intel to create a new product segment based off of LNL. Client is now their main revenue stream, hanging onto it should be among its top priorities. To kill off a successful product segment for BOM optimization is a mistake. If LNL is a sales success, they could charge more to offset the higher costs.
 
Reactions: Thibsie
sale-70-410-exam    | Exam-200-125-pdf    | we-sale-70-410-exam    | hot-sale-70-410-exam    | Latest-exam-700-603-Dumps    | Dumps-98-363-exams-date    | Certs-200-125-date    | Dumps-300-075-exams-date    | hot-sale-book-C8010-726-book    | Hot-Sale-200-310-Exam    | Exam-Description-200-310-dumps?    | hot-sale-book-200-125-book    | Latest-Updated-300-209-Exam    | Dumps-210-260-exams-date    | Download-200-125-Exam-PDF    | Exam-Description-300-101-dumps    | Certs-300-101-date    | Hot-Sale-300-075-Exam    | Latest-exam-200-125-Dumps    | Exam-Description-200-125-dumps    | Latest-Updated-300-075-Exam    | hot-sale-book-210-260-book    | Dumps-200-901-exams-date    | Certs-200-901-date    | Latest-exam-1Z0-062-Dumps    | Hot-Sale-1Z0-062-Exam    | Certs-CSSLP-date    | 100%-Pass-70-383-Exams    | Latest-JN0-360-real-exam-questions    | 100%-Pass-4A0-100-Real-Exam-Questions    | Dumps-300-135-exams-date    | Passed-200-105-Tech-Exams    | Latest-Updated-200-310-Exam    | Download-300-070-Exam-PDF    | Hot-Sale-JN0-360-Exam    | 100%-Pass-JN0-360-Exams    | 100%-Pass-JN0-360-Real-Exam-Questions    | Dumps-JN0-360-exams-date    | Exam-Description-1Z0-876-dumps    | Latest-exam-1Z0-876-Dumps    | Dumps-HPE0-Y53-exams-date    | 2017-Latest-HPE0-Y53-Exam    | 100%-Pass-HPE0-Y53-Real-Exam-Questions    | Pass-4A0-100-Exam    | Latest-4A0-100-Questions    | Dumps-98-365-exams-date    | 2017-Latest-98-365-Exam    | 100%-Pass-VCS-254-Exams    | 2017-Latest-VCS-273-Exam    | Dumps-200-355-exams-date    | 2017-Latest-300-320-Exam    | Pass-300-101-Exam    | 100%-Pass-300-115-Exams    |
http://www.portvapes.co.uk/    | http://www.portvapes.co.uk/    |