The 3rd slide that mvprod posted is specifically for comparing IPC, so Geekerwan limited the clocks to about 4 GHz. The other slides are measuring at max frequency, I believe.
The 3rd slide that mvprod posted is specifically for comparing IPC, so Geekerwan limited the clocks to about 4 GHz. The other slides are measuring at max frequency, I believe.But even the bottom graph the results of each aren’t anywhere near max clocks. The X Elite can hit 4.3GHz and yet it’s only being measured at 3.8GHz for both int and fp.
Only reason why I can think of is that it’s showing the peak point of IPC. For example for FP the M4 above scores 15.58 at 3.87GHz for 4.03pts/GHz.. but its max of 16.11 at 4.04GHz is 3.98pts/GHz.
But nonetheless it’s probably best to show the results at max clocks such that overall performance is shown. Or like I said before delineate between different datasets to show max IPC vs performance at max clocks.
Yeah I guess that’s true (about the 4GHz comparison).The 3rd slide that mvprod posted is specifically for comparing IPC, so Geekerwan limited the clocks to about 4 GHz. The other slides are measuring at max frequency, I believe.
Well spotted. There seems to be some issues with the data/curves.Yeah I guess that’s true (about the 4GHz comparison).
But the two charts above don’t really show that because like I noted in my first post about this, the X Elite only goes up to around 9 points in fp in the second slide whereas we know it can go higher than 13.58 in the bottom slide.
What would explain the disconnect there? Maybe he’s running a different compiler?
Oryon V2 is rumoured to hit 5 GHz. Do you think it can be dine without adding more pipeline stages?
Also Apple M5 will be around 5 GHz too, I think (M1 = 3.2, M2 = 3.5, M3 = 4.05, M4 = 4.5).
Mahua (X2 Elite?) is 6L + 6M CPU. Is that not low power?and then Qualcomm needs to make a low power design which next gen X Elite isn’t going be.
I do think 5 GHz is probable for Snapdragon X2, though I find it unbelievable that 8 Gen 5 will also hit 5 GHz.I don’t it will be Qualcomm who Intel should be worried about although that 5GHz core if it that happens and its efficient then it’s different.
| Node | Peak Clock | ST power | |
| X Elite | N4P | 4.32 GHz | 18 W |
| 8 Gen 4 | N3E | 4.3 GHz | ??? |
TSMC really is expensive. But also speaks about how QCOM has been increasing die size gen over gen.Qualcomm SoC price trend:
View attachment 108614
There is a rumored automotive SoC (SA8797) with 18 CPU cores that shares the rumored core count of the Glymur SoC with up to 800 GB/s memory bandwidth (16x 16-bit LPDDR controllers), 320 TOP/s of inference performance and 8.1 TFLOP/s GPU performance (even 1.4 TOP/s of INT8 on audio), it's possible that the PC oriented Glymur is based on this SoC with a different memory config. to spread NRE costs. (Not sure they can stretch their legs budget-wise at Q as much Apple did with separate designs for A18/A18 Pro rather than die harvesting...)Mahua (X2 Elite?) is 6L + 6M CPU. Is that not low power?
View attachment 108613
I do think 5 GHz is probable for Snapdragon X2, though I find it unbelievable that 8 Gen 5 will also hit 5 GHz.
The question is can they do it without blowing up the power consumption to the moon, regressing cache latencies, etc...
PS:
Node Peak
ClockST power X Elite N4P 4.32 GHz 18 W 8 Gen 4 N3E 4.3 GHz ???
It will be very interesting to see how power 8G4 consumes for ST.
It will show what degree of improvements Qualcomm has made 1 year later to Oryon, and confirm/deny theories that there is some kind of defect/bug in X Elite silicon that's causing the high power consumption.
It’s not just TSMC. No one can make cheap chips in $100B + foundries using EUV machines. Cost reduction as a part of node advances ended at about the 22 nm - 14 nm timeframe. Since the (virtual) 7 nm node, the costs are astronomical.TSMC really is expensive. But also speaks about how QCOM has been increasing die size gen over gen.
That sounds beastly. I didn't know that automotive SoCs had to be so powerful. One question though; 16 × 16 is a 256 bits... How do you get 800 GB/s with a 256 bit LPDDR controller? It's impossible even with the latest LPDDR5X-10667 standard.There a rumored automotive SoC (SA8797) with 18 CPU cores that shares the rumored core count of the Glymur SoC with up to 800 GB/s memory bandwidth (16x 16-bit LPDDR controllers), 320 TOP/s of inference performance and 8.1 TFLOP/s GPU performance (even 1.4 TOP/s of INT8 on audio), it's possible that the PC oriented Glymur is based on this SoC with a different memory config.
You're right, that detail sounds incorrect. It's more likely a 16 x (4 x 16) bit interface. Q already has products that likely have this memory controller config. in their latest AI 100 Ultra:That sounds beastly. I didn't know that automotive SoCs had to be so powerful. One question though; 16 × 16 is a 256 bits... How do you get 800 GB/s with a 256 bit LPDDR controller? It's impossible even with the latest LPDDR5X-10667 standard.
Qualcomm considers Oryon’s 12 MB L2 a very large capacity integrated cache. Latency is 15-20 cycles depending on which part of the cache data is in. That suggests the L2 is built from multiple slices, much like the L3 cache in Intel and AMD’s architectures.
I'd really like to see such sliced L2 on consumer (especially laptop) chips on the x86 side as well.@naukkis
Chips and Cheese suggests that the L2 cache in X Elite may not be a unified one, but a sliced one;
Hot Chips 2024: Qualcomm’s Oryon Core
Today, Qualcomm is presenting on their Oryon core.chipsandcheese.com
@naukkis
Chips and Cheese suggests that the L2 cache in X Elite may not be a unified one, but a sliced one;
Hot Chips 2024: Qualcomm’s Oryon Core
Today, Qualcomm is presenting on their Oryon core.chipsandcheese.com
Probably something in between is true here: the X-Elite SoC has 3x 4-CPU clusters which are each powered on in an all or nothing fashion. Each CPU can use the entire cluster's L2, but is best matched to a particular subset of that cluster's rather large L2.Sliced L3 like in x86 cpus meas that every core have a slice of cache and interconnect to other slices. X elite like Intel E-cores and AMD Dozers L2 aren't sliced like that, unified L2 serves multiple cores. That unified L2 though can have slices that has different access times to different cores - likely preferring closest to cpu part of cache prioritized. That kind of unified cache can power gate it's not needed parts when executing lighter jobs - unlike x86 like sliced cache where working cpu needs to power up all cache slices(because memory addresses are interleaved between slices) and interconnect network between them.
Ironic that they seem to be much more successful taking Intel (Mobileye) ADAS market share rather than Laptops.
Qualcomm has one of the lower PE ratios in the industry. 22 vs AMD's 205, for example.I wonder how much actual profit that is? They were never going to justify their lofty valuation just by continuing to dominate smartphones, or even if Qualcomm could carve off a small slice of PCs. Maybe they think the auto market can.
I wonder if it would be prudent for Qualcomm to do some kind of refresh of the X Elite, fixing those deficiencies porting it to 3nm, for a release in 2025H1. X Elite 2nd gen is tipped for 2026H1, which is a long time away. Ming Chi Kuo suggested something like that;The 1st gen X-Elite design allegedly used a rushed redesign of a server targeted CPU (also plagued by IP protection related redesigns related to ARM's lawsuit against Nuvia per Qualcomm's court filings). As such, it does not sport more granular power gating features like DVFS, E-cores or per core power gating which we may see starting with the 8G4.
The X Elite and X Plus chips, used for Windows on ARM (WOA), will reach about 2 million unit shipments in 2024, with expected year-on-year growth of at least 100–200% in 2025. The X Elite and X Plus will have modified versions in 2025, with a reduction in end product prices.
That’s kind of what I was alluding to in the Mediatek thread. We can already tell that S8G4 looks better than the X Elite. A quick refresh to align the core characteristics at a minimum doesn’t seem out of the question. And Oryon v2 perhaps could be released earlier as it was less prone to delay as v1.I wonder if it would be prudent for Qualcomm to do some kind of refresh of the X Elite, fixing those deficiencies porting it to 3nm, for a release in 2025H1. X Elite 2nd gen is tipped for 2026H1, which is a long time away. Ming Chi Kuo suggested something like that;
Two new growth drivers for Qualcomm / Qualcommçå©åæ°æé·åè½
The SM8750 (Snapdragon 8 Gen 4), which will enter mass production in 2H24, is expected to be priced 25â30% higher than the current flagshipâ¦medium.com
Qualcomm has one of the lower PE ratios in the industry. 22 vs AMD's 205, for example.
But yeah I'm not sure how much growth that market will really have. The expectations seem overstated.
Die harvested 8G4's (e.g. ones w/ a busted modem block) could also be very potent laptop chips with better efficiency characteristics than the X-Elite/Plus at 3nm with a major design refresh, but it's difficult to see where they would slot them in with the released X-Elite and X-Plus laptop parts. An 8G4 is likely to have a stronger GPU, but a weaker CPU in multi-threaded situations than the laptop parts. Maybe budget gaming laptops and Steam deck competitors...I wonder if it would be prudent for Qualcomm to do some kind of refresh of the X Elite, fixing those deficiencies porting it to 3nm, for a release in 2025H1. X Elite 2nd gen is tipped for 2026H1, which is a long time away. Ming Chi Kuo suggested something like that;
Two new growth drivers for Qualcomm / Qualcommçå©åæ°æé·åè½
The SM8750 (Snapdragon 8 Gen 4), which will enter mass production in 2H24, is expected to be priced 25â30% higher than the current flagshipâ¦medium.com