Wonder when they will figure out that the world have turned upside down 🧐
It would seem with this new TSV layout, the V$ die most certainly has to cover some of the area of the cores, which would be a cooling disaster if it were on top. Seems to lend credibility to the idea they are putting it underneath now - No longer any physical size constraints on the V$ die to fit only above the L3 block on the CCD. This could mean they are free to make the V$ die larger without any cooling implications.Zen 5 die: TSV's to the 64 MB X3D L3 cache:
It simply must have enough and well distributed TSV's...
It looks like a all the TSV's providing the power to the X3D L3 die are using an MIM decoupling capacitor for each power and ground pair of TSV's leading to something like an extra ~8500 power/ground TSV's. Under each black square should be two TSV's.
Original die photos: https://www.flickr.com/photos/130561288@N04/
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I'd venture to bet at this point its about a 99% probability that its under the CCD. Question is now, how high of a boost clock does that allow for on Zen 5? 5.4 and 5.6 perhaps?It would seem with this new TSV layout, the V$ die most certainly has to cover some of the area of the cores, which would be a cooling disaster if it were on top. Seems to lend credibility to the idea they are putting it underneath now - No longer any physical size constraints on the V$ die to fit only above the L3 block on the CCD. This could mean they are free to make the V$ die larger without any cooling implications.
Then, the problem would be power delivery to the cores.It would seem with this new TSV layout, the V$ die most certainly has to cover some of the area of the cores, which would be a cooling disaster if it were on top. Seems to lend credibility to the idea they are putting it underneath now - No longer any physical size constraints on the V$ die to fit only above the L3 block on the CCD. This could mean they are free to make the V$ die larger without any cooling implications.
It does seem like there are twice as many power TSVs vs. ring bus TSVs in that breakdown. Can't imagine a piece of cache needs that many power plane connections.Then, the problem would be power delivery to the cores.
Or, would those TSVs be delivering power to the core through the V-Cache?
There is no way they are changing from flip chip packaging. They still have an organic sub strait that needs complex analogy data transfer. Your making that harder for something you think is a problem.
Do any of you even own a zen4 x3d ... Cooling is not the issue. Look at zen5 tdps , again cooling won't be the issue. It is voltage.
Thermals are very much an issue. This is why even with reduced voltages and clocks, they had to reduce the thermal target from 95C to 89C.There is no way they are changing from flip chip packaging. They still have an organic sub strait that needs complex analogy data transfer. Your making that harder for something you think is a problem.
Do any of you even own a zen4 x3d ... Cooling is not the issue. Look at zen5 tdps , again cooling won't be the issue. It is voltage.
It would seem with this new TSV layout, the V$ die most certainly has to cover some of the area of the cores, which would be a cooling disaster if it were on top. Seems to lend credibility to the idea they are putting it underneath now - No longer any physical size constraints on the V$ die to fit only above the L3 block on the CCD. This could mean they are free to make the V$ die larger without any cooling implications.
This "thermal transfer optimized" silicon is quite thin. There is not a lot to optimize.¹The only reason it works at all is because they carefully designed it so the V$ die didn't overlap the cores and placed thermal transfer optimized silicon over them.
the CCX to IOD connection is an analogy very high speed interfaceThe only thing going to CCD is power and infinity fabric. All the analog is coming from the IO die.
It does seem like there are twice as many power TSVs vs. ring bus TSVs in that breakdown. Can't imagine a piece of cache needs that many power plane connections.
This is only true if you assume the outermost TSV line is the edge of the V$ chip. I think it doesn't make sense physically or layout-wise for this to be the case. I believe the V$ die boundary would stretch beyond the edge TSV by some meaningful amount, covering much more than the small portion of the core next to the L1/L2.The cache die underneath the CCD is just impossible with this CCD and package.
Also the "core part" that is overlapped still has ~75% RAM and ~25% logic, which is better visible in the hi-res image.
I'm sure that they modeled the local heath generation during the design phase to make sure that it isn't a problem.
If the cache die is smaller, why do the TSV's extend so far into the cores?The cache die is probably smaller this time as well as the same savings on the ccd side could be expected on the cache die.
If the cache die is smaller, why do the TSV's extend so far into the cores?
It allowed a smaller L3 which is beneficial even if the cache chip is the same in other ways.So, we are excited, cause something has changed, but we dont know why and whether the change provides any benefit to us, as the customers? Am i getting that right?