It can be argued that we discuss MediaTek competition, though I agree I might have gone a bit too farIs this the MediaTek thread? or the Apple thread?
If it's taping out this month, it's gotta be using the Cortex X925 core, not it's successor surely?According to reports from leakers on the Chinese social media site Weibo, Mediatek and Nvidia are collaborating on a 3nm AI CPU. IT Home shared a report from user "Mobile Chip Expert" today, claiming that the CPU is entering the tape-out phase of production this month, with mass production on track for late 2025.
There will be no growth until there is enough optimised software.Nvidia and MediaTek collaborate on 3nm AI PC CPU — chip reportedly ready for tape-out this month
Years of rumors may finally prove true.www.tomshardware.com
If it's taping out this month, it's gotta be using the Cortex X925 core, not it's successor surely?
Mass production in late 2025 doesn't sound good either. That means it will come to laptops in early 2026. Basically launching alongside the 2nd generation Snapdragon X. I thought Mediatek/Nvidia might release it sometime in 2025 itself. It would have been strategic if they did so.
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If that rumour is true, both Snapdragon X 2nd gen and Mediatek/Nvidia's SoC will be coming to notebooks in 2026. I don't think there'll be any significant growth in ARM notebook marketshare in 2025.
Just is what is about to pull Huawei in their Harmony Os NextThere will be no growth until there is enough optimised software.
One could do that with 32-bit Arm.
I still haven't come around to accepting the fact that is reusing last year's microarchitectures for 7 out of the 8 CPU cores in the Dimensity 9400. Puzzling.The 9400 is equipped with one Arm Cortex-X925 core with a peak frequency of 3.62GHz, three Cortex-X4 cores reaching up to 3.3GHz, and four Cortex-A720 cores with a maximum frequency of 2.4GHz.
The A720s were reworked and has a different performance curve. I forgot which one, but one poster claimed the Geekerwan video showed virtually the same performance as Apple’s e core for virtually the same power in SPEC. I didn’t notice that and have been planning to rewatch it.MediaTek confident Dimensity 9400 can compete with Qualcomm
MediaTek has officially launched its Dimensity 9400 chipset, which it is confident can compete with Qualcomm's Snapdragon 8 Gen 4, launching later this month.www.digitimes.com
~1 week to see if their confidence was placed right, or not.
I still haven't come around to accepting the fact that is reusing last year's microarchitectures for 7 out of the 8 CPU cores in the Dimensity 9400. Puzzling.
| Room Temperature | Refrigerator | Room Temperature + Renamed Geekbench Package | Refrigerator + Renamed Geekbench Package | |
| Single-Core | 2735 | 2910 | 2372 | 2772 |
| Multi-Core | 8507 | 9094 | 7776 | 8651 |
In fact, vivo promises even higher results, but since our unit is running a pre-production software, we will have to re-test once we have more time to spend with the X200 Pro, so stay tuned for the full review.
Maybe D8400 will be the one?Dimensity 9300 flagship chip introduced the first all OoO CPU design for Android phones. Dimensity 9400 is the 2nd generation and follows on the heels of it's predecessor.
The next step should be to bring the all OoO design to midrange SoCs.
| L2 per core | L3 | |
| X Elite Oryon | 3 MB | None |
| M4 P-core | 4 MB | None |
| M3 Max P-core | 2.66 MB | None |
| Cortex X925 | upto 3 MB | upto 32 MB |
(Speculation)
High End Laptop CPU ala Strix/X Elite
X925 (3 MB L2) @ 4.0 GHz × 2
X925 (2 MB L2) @ 3.6 GHz × 8
A725 (1 MB L2) @ 2.4 GHz × 4
32 MB L3
16 MB SLC
Total Cache = 74 MB
Mid End Laptop CPU ala LNL/X Plus
X925 (3 MB L2) @ 4.0 GHz × 1
X925 (2 MB L2) @ 3.6 GHz × 3
A725 (1 MB L2) @ 2.4 GHz × 4
16 MB L3
8 MB SLC
Total Cache = 37 MB
A CPU with stock ARM cores can be kitted out with crazy amounts of cache.
For comparison, the total caches of X Elite, M4 and Lunar Lake respectively are 42 MB, 28 MB and 34 MB.
*Total Cache = L2 + L2 + SLC
@naukkis It seems Qualcomm/Apple's simple L1/L2 two-tier CPU cache hierarchy is also more 'capacity efficient'.
L2 per core L3 X Elite Oryon 3 MB None M4 P-core 4 MB None M3 Max P-core 2.66 MB None Cortex X925 upto 3 MB upto 32 MB
ARM's latest X925 core can be configured with as much L2-per-core as Qualcomm/Apple, but ARM's L2 is private to each core, whereas in Qualcomm/Apple designs it's shared among a cluster of cores. ARM also needs to have an L3 cache on top of that, which seems wasteful.
How about a Low end Laptop with...(Speculation)
High End Laptop CPU ala Strix/X Elite
X925 (3 MB L2) @ 4.0 GHz × 2
X925 (2 MB L2) @ 3.6 GHz × 8
A725 (1 MB L2) @ 2.4 GHz × 4
32 MB L3
16 MB SLC
Total Cache = 74 MB
Mid End Laptop CPU ala LNL/X Plus
X925 (3 MB L2) @ 4.0 GHz × 1
X925 (2 MB L2) @ 3.6 GHz × 3
A725 (1 MB L2) @ 2.4 GHz × 4
16 MB L3
8 MB SLC
Total Cache = 37 MB
A CPU with stock ARM cores can be kitted out with crazy amounts of cache.
For comparison, the total caches of X Elite, M4 and Lunar Lake respectively are 42 MB, 28 MB and 34 MB.
*Total Cache = L2 + L2 + SLC
@naukkis It seems Qualcomm/Apple's simple L1/L2 two-tier CPU cache hierarchy is also more 'capacity efficient'.
L2 per core L3 X Elite Oryon 3 MB None M4 P-core 4 MB None M3 Max P-core 2.66 MB None Cortex X925 upto 3 MB upto 32 MB
ARM's latest X925 core can be configured with as much L2-per-core as Qualcomm/Apple, but ARM's L2 is private to each core, whereas in Qualcomm/Apple designs it's shared among a cluster of cores. ARM also needs to have an L3 cache on top of that, which seems wasteful.
This would have large cache and 3nm-only cores. That's high-end laptop territory.Mid End Laptop CPU ala LNL/X Plus
X925 (3 MB L2) @ 4.0 GHz × 1
X925 (2 MB L2) @ 3.6 GHz × 3
A725 (1 MB L2) @ 2.4 GHz × 4
16 MB L3
8 MB SLC
Total Cache = 37 MB
A CPU with stock ARM cores can be kitted out with crazy amounts of cache.
I expected that since SD 7 one will go with all OoO core design and if the situacion with ARM happens... Series 6 and 4 will happen the same with the config you mentioned. The issue? Cost might increase a little, but more the energy consumption.@DZero your dreams may have come true.
Rumour:
View attachment 110635
Dimensity 8400 will have 8 × A725 cores?
Ahem...I expected that since SD 7 one will go with all OoO core design and if the situacion with ARM happens... Series 6 and 4 will happen the same with the config you mentioned. The issue? Cost might increase a little, but more the energy consumption.
Seems that the in-order core era is about to end.
And indeed... I expect some configs.
Potential 1:
4 x A725 - 3.2 Ghz - 4 MB L2 Cache
4 x A725 - 2.0 Ghz - 2 MB L2 Cache
L3 Cache - 12 MB
Potential 2:
2 x A725 - 3.6 Ghz - 4 MB L2 Cache
6 x A725 - 2.0 Ghz - 3 MB L2 Cache
L3 Cache - 8 MB
But the Potential 2 might end being the Dimensity 7400 if goes all OoO config