Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

AMDK11 · Oct 13, 2024

DavidC1 said:
Are you saying Skymont, which is on the same ring and die won't also benefit or be harmed from the changes?

The LNC 9% number and SKL 32/72% number is on the same die is it not?

Zen 5 clocks identically in peak to Arrowlake. Both at 5.7GHz. Yet Zen 5 despite being on a significantly less dense node(50-60% difference) is about the same size as Lion Cove.

It looks like this:
LionCove has more advanced logic than Zen 5 but suffers from cache delays. Although the predictor is more advanced, it is weaker than GoldenCove in some respects. It's more or less a draw Zen5 vs LionCove. But this is from the LunarLake version.

We'll see what the analysis shows after testing for ArrowLake.

Hulk · Oct 13, 2024

AMDK11 said:
Bloated because it can run at 5.7 GHz. look at Zen4c which while maintaining the same IPC as Zen4, is much smaller than Zen4.

The same applies to Skymont, which has a much simpler design and achieves lower clock speeds, thanks to which it can occupy a much smaller area. In other words, Skymont has a much denser logical packing per mm2.

And now Skymont from a different angle. Gracemont without HT and at a much lower clock speed has roughly the IPC of Skylake from 2015. Skymont has 32% higher IPC INT and 70% higher FP after 9 years of catching up to GoldenCove from 2021! Do you still say it's a breakthrough?

The year is 2024 and Skymont is at the level of the 2021 GoldenCove IPC, with a much lower clock speed and no HT.

I don't think it's as groundbreaking as you make it out to be. Sure, Skymont with 16 cores + 8 P-Core cores gives a very efficient processor in total. But painting Skymont as a revolution is a bit weak. Wait for ArrowLake's independent testing and then we'll make our final assessment.

However, despite some leaks, I believe that E-Core and P-Core will be consistent and adapted to specific geometries in the future.

I'm not following. Gracemont in 2021 was equal to the P core, Skylake of 2105. That's the E core team being 6 years behind the P team.

Now it looks as though 2024 Skymont will equal the performance of 2021 Golden Cove. That's the E team only being 3 years behind the P team. I read your timeline as showing Skymont is somewhat of a wonder. I never thought of it that way but I like the analogy of the E team trying to catch the P team and the P team trying to stay ahead.

LightningZ71 · Oct 13, 2024

It's hard not to think that arrow lake wouldn't do notably better on all of the MT benchmarks if they had gone with a 6+24/30 thread design instead of an 8+16/24 thread design. ST would have been unaffected. Low thread MT tasks coukd have been distributed as one per quad mont cluster if they scaled past 6 threads. High thread tasks would have outstripped AMD's 16/32 designs.

Hulk · Oct 13, 2024

I'm sorry to break the train of thought but what were the differences between Raptor Cove and Redwood Cove again?

OneEng2 · Oct 13, 2024

AMDK11 said:
Bloated because it can run at 5.7 GHz. look at Zen4c which while maintaining the same IPC as Zen4, is much smaller than Zen4.

The same applies to Skymont, which has a much simpler design and achieves lower clock speeds, thanks to which it can occupy a much smaller area. In other words, Skymont has a much denser logical packing per mm2.

And now Skymont from a different angle. Gracemont without HT and at a much lower clock speed has roughly the IPC of Skylake from 2015. Skymont has 32% higher IPC INT and 70% higher FP after 9 years of catching up to GoldenCove from 2021! Do you still say it's a breakthrough?

The year is 2024 and Skymont is at the level of the 2021 GoldenCove IPC, with a much lower clock speed and no HT.

I don't think it's as groundbreaking as you make it out to be. Sure, Skymont with 16 cores + 8 P-Core cores gives a very efficient processor in total. But painting Skymont as a revolution is a bit weak. Wait for ArrowLake's independent testing and then we'll make our final assessment.

However, despite some leaks, I believe that E-Core and P-Core will be consistent and adapted to specific geometries in the future.

This exactly. Lets remember here, it isn't like Skymont has any fewer transistors than Golden Cove (my guess). Skymont is just way more dense due to a much better process node.

It also isn't like Skymont performs as well as Lion Cove in all work loads either. If this were even POSSIBLE, everyone would be designing cores like this for everything. It isn't like Intel's E Core team is the ONLY processor engineering team on the planet that has very smart people.

AMDK11 said:
Contrary to what others say, including DavidC1, I argue that LionCove is the first major redesign in the transition from a monolithic to a tiled structure, and therefore loses latency between tiles and, in particular, access to the RAM controller. LionCove is the first project to use new design tools and methods along with reducing overall power consumption for ArrowLake. We will evaluate this in independent tests.

... and I think that Intel has been late to this game as they have been able to absorb the large die penalty in their own vertically integrated fab. Now they are doing some catch up in the tile/chiplet game as they work out their processor design work-arounds for the interconnect latency issues they now have to deal with.

Additionally, the day of the heterogenous core is over. More and more specialized cores and fancy OS scheduling will be the future. It has always been the case that you can make a MUCH faster processor for a SPECIFIC task than you can make a general purpose processor. Doing this not only gets you TONS more performance, it does so at a fraction of the die size.

Sure, today we are only talking very simple "P core" and "E Core" designs. In the future there will be MORE specific core designators for more specific loads. These designs will be more space efficient AND more thermally efficient. I am declaring it here .... Homogenous processor design is dead guys.

cannedlake240 · Oct 13, 2024

AMDK11 said:
Gracemont without HT and at a much lower clock speed has roughly the IPC of Skylake from 2015.

Skymont isn't revolutionary but it seems to be roughly matched with recent AMD architectures which are often praised for PPA. Granted there's obviously no guarantee that Atom would compete just as well in the P core league if Intel was to greenlight such a design

DavidC1 · Oct 13, 2024

AMDK11 said:
And now Skymont from a different angle. Gracemont without HT and at a much lower clock speed has roughly the IPC of Skylake from 2015. Skymont has 32% higher IPC INT and 70% higher FP after 9 years of catching up to GoldenCove from 2021! Do you still say it's a breakthrough?

So what are you saying? It took 9 years for the P core team to get 45% while it took the E core team just 3 years? Hmm...

Let's ignore the 10nm fiasco and look at it post Icelake.

2019 Icelake: Sunny Cove is 18% faster.
2020 Tremont: 32% faster
2021 Alder: 19% faster Golden, and 30% faster Grace. Grace = SKL in Int
2024 Arrow: 9% faster Lion, 32%/72% faster Skymont. Sky = GLC in Int and FP

So between 2019 and now, the P core got 1.18 x 1.19 * 1.09 = 53% per clock.

At the same time frame the E core got 1.32 x 1.30 x (1.32/1.72) = 127% in Int and 195% in FP.

OneEng2 said:
By your logic, it should be possible using the same process for the P core team to increase the performance by 400% (4 Skymont cores fit into the same size as 1 Lion Cove core .... or close enough). If it were this easy, AMD, Apple, and literally everyone else would be having cores that dwarfed both Intel and AMD in single threaded performance.

Of course not. But let's just compare to AMD. It is 50% larger than Zen 5.

What do you think an AMD core that's 50% bigger than Zen 5 would do hmm?

igor_kavinski · Oct 13, 2024

Hulk said:
I'm sorry to break the train of thought but what were the differences between Raptor Cove and Redwood Cove again?

Summary from CnC article:

General Overview

Incremental Upgrade: Redwood Cove is primarily a minor upgrade from Raptor Cove, continuing to leverage the fundamentals of Golden Cove.

Optimizations: While the core structure sizes largely remain unchanged, there are notable optimizations and enhancements in the architecture.

Frontend Improvements

Branch Prediction: Enhanced branch prediction capabilities improve accuracy and reduce misprediction recovery latency. The predictor can recognize longer patterns than previous architectures.

Instruction Cache: The L1 instruction cache capacity has been doubled to 64 KB, which enhances instruction delivery speed and efficiency.

Micro-op Cache: The size of the Instruction Decode Queue (IDQ) has increased to 192 entries, allowing better management of micro-ops during execution.

Instruction Fetch and Decode

Macro Fusion: New instructions for better macro fusion have been introduced, allowing efficient execution of dependent operations that can reduce the number of micro-ops needed.

Latency Improvements: The backend execution units see a reduction in latency for floating-point multiplications, now at 3 cycles.

Memory and Cache Enhancements

L2 Cache: The mid-level L2 cache size has been maintained at 2 MB, similar to Raptor Lake, aiding performance.

Memory Bandwidth: Improvements include a deeper mid-level cache miss queue (increased from 48 to 64 entries) and better LLC page prefetching capabilities.

Prefetching Strategy: An LLC page prefetcher can now prefetch two 4 KB pages, increasing the chances of hitting required data before it is requested by the CPU.

Simultaneous Multi-Threading (SMT)

Enhanced SMT Performance: Redwood Cove features several improvements in how resources are allocated and managed between threads, achieving up to a 17.6% increase in throughput for SPEC CPU2017’s integer tests.

OneEng2 · Oct 13, 2024

Hulk said:
The discussion regarding P and E cores is interesting.
Is Lion Cove a failure because it only achieves an average 9% IPC increase? Obviously the question is subjective in nature but I think we need to keep in mind that Lion Cove has to deal with the penalty of moving from monolithic to tiles and it looks like Zen 4 to 5 is underperforming from an IPC point-of-view. Maybe there isn't much low hanging fruit left in the design?

Is the huge IPC gain in moving from Crestmont/Gracemont to Skymont a sign that the basic architecture is "better" or there is more low hanging fruit in that design and it will soon top out IPC-wise as well? Skymont is looking magnificent, no doubt about it, especially considering how area efficient it is, but is does have a 20% clock deficit vs. Lion Cove. How much smaller could LC have been if it topped out at 4.6GHz.

I believe we are witnessing the huge cost both in terms of R&D and economics (die area) of very high ST performance. The problem is that there is still plenty of software that requires performant ST cores. Do YOU need 8 of them? Or only 4? Or do you need 12? That of course depends on what each of us considers our primary workloads.

Intel has a good "solution" for MT but alas software development is not quite there yet. If it were and MT was all that mattered then we'd be seeing Arrow Lake having 40 Skymont cores.

Finally, I ask the more knowledgable microprocessor architects here what is the limit for ST performance? I understand this will vary based on the code, but how much instruction parallelism exists in the code? How much and how accurately can you predict what will happen down the line as instructions are processed? Seems like looking into the future and "being ready" for what comes next is getting quite costly in terms of both transistors and ramping up clockspeed, which seem to be the only way to increase ST performance.

Theoretically speaking is there a formula that gives an indication of a limit to ST performance for microprocessors? Or a graph of some sort to indicate ST performance vs number of transistors or something like that?

Great questions.

Where do you draw the line?

OneEng2 · Oct 13, 2024

DavidC1 said:
So what are you saying? It took 9 years for the P core team to get 45% while it took the E core team just 3 years? Hmm...

Let's ignore the 10nm fiasco and look at it post Icelake.

2019 Icelake: Sunny Cove is 18% faster.
2020 Tremont: 32% faster
2021 Alder: 19% faster Golden, and 30% faster Grace. Grace = SKL in Int
2024 Arrow: 9% faster Lion, 32%/72% faster Skymont. Sky = GLC in Int and FP

So between 2019 and now, the P core got 1.18 x 1.19 * 1.09 = 53% per clock.

At the same time frame the E core got 1.32 x 1.30 x (1.32/1.72) = 127% in Int and 195% in FP.

Of course not. But let's just compare to AMD. It is 50% larger than Zen 5.

What do you think an AMD core that's 50% bigger than Zen 5 would do hmm?

LMAO. Ok, good point. You could have pounded me even more by pointing out that Lion Cove is on a more dense N3B process as opposed to Zen 5 on N4P. Touché.

DavidC1 · Oct 13, 2024

AMDK11 said:
It looks like this:
LionCove has more advanced logic than Zen 5 but suffers from cache delays. Although the predictor is more advanced, it is weaker than GoldenCove in some respects. It's more or less a draw Zen5 vs LionCove. But this is from the LunarLake version.

We'll see what the analysis shows after testing for ArrowLake.

And what did those dramatically larger structures resulting in 50% larger core size give Lion Cove over Zen 5?

Nothing. Nada. Zero. Results>>>specs

Clearly there are low level details that make Zen 5 better than high level. You keep bringing up the cache changes, but it doesn't prevent the E core from performing 32%/72% better than the predecessor.

As enthusiasts don't we always look for Apples vs. Apples comparisons? Whatever cripples Lion Cove would also cripple Skymont.

cannedlake240 said:
Skymont isn't revolutionary but it seems to be roughly matched with recent AMD architectures which are often praised for PPA. Granted there's obviously no guarantee that Atom would compete just as well in the P core league if Intel was to greenlight such a design

An architecture that introduced novel decoder to address x86's fundamental weakness and a few years after the competitor is adopting is not far off from being dramatically better. "Revolutionary" architectures hardly work out in practice. Itanium was revolutionary. Bulldozer wasn't but a huge departure from the past. So was Netburst.

AMDK11 · Oct 13, 2024

Hulk said:
I'm not following. Gracemont in 2021 was equal to the P core, Skylake of 2105. That's the E core team being 6 years behind the P team.

Now it looks as though 2024 Skymont will equal the performance of 2021 Golden Cove. That's the E team only being 3 years behind the P team. I read your timeline as showing Skymont is somewhat of a wonder. I never thought of it that way but I like the analogy of the E team trying to catch the P team and the P team trying to stay ahead.

This will depend on future generations of P-Core, and since both teams are now on one team, I think the designs will be more balanced.

DavidC1 · Oct 13, 2024

OneEng2 said:
LMAO. Ok, good point. You could have pounded me even more by pointing out that Lion Cove is on a more dense N3B process as opposed to Zen 5 on N4P. Touché.

I don't really care about winning arguments. I care about truth.

They are actually quite close in size. But Lion Cove is on N3B, which is substantially denser than N4P. I don't know the exact differences. But 50% is a good figure.

What does Intel get from a core that's 50% larger?

Also Skymont's 1.15mm2 core size is quite a bit smaller than Zen 5C even normalized to process I would say.

AMDK11 · Oct 13, 2024

Hulk said:
I'm sorry to break the train of thought but what were the differences between Raptor Cove and Redwood Cove again?

RedwoodCove and LionCove have the same number of uop decoding queues with 192 entries compared to 144 in GoldenCove and 64KB L1-I each versus 32KB in GoldenCove. These are the main changes RedwoodCove.

DavidC1 · Oct 13, 2024

Hulk said:
I'm not following. Gracemont in 2021 was equal to the P core, Skylake of 2105. That's the E core team being 6 years behind the P team.

Gracemont was noticeably behind Skylake in FP. The doubled FP capability practically eliminates that disadvantage.

So it went from being ~ on Int and behind in FP compared to a 2015 core to being ~ on both Int and FP in 2021.

poke01 · Oct 13, 2024

Run CB2024 only on SKT to find out the Skymont performance in FP.

AMDK11 said:
Contrary to what others say, including DavidC1, I argue that LionCove is the first major redesign in the transition from a monolithic to a tiled structure, and therefore loses latency between tiles and, in particular, access to the RAM controller. LionCove is the first project to use new design tools and methods along with reducing overall power consumption for ArrowLake. We will evaluate this in independent tests.

do we really? Redwood cove did it first?

DavidC1 said:
Gracemont was noticeably behind Skylake in FP. The doubled FP capability practically eliminates that disadvantage.

So it went from being ~ on Int and behind in FP compared to a 2015 core to being ~ on both Int and FP in 2021.

so logically speaking then the 2026 e-core will surpass Lion cove?

AMDK11 · Oct 13, 2024

DavidC1 said:
And what did those dramatically larger structures resulting in 50% larger core size give Lion Cove over Zen 5?

Nothing. Nada. Zero. Results>>>specs

Clearly there are low level details that make Zen 5 better than high level. You keep bringing up the cache changes, but it doesn't prevent the E core from performing 32%/72% better than the predecessor.

As enthusiasts don't we always look for Apples vs. Apples comparisons? Whatever cripples Lion Cove would also cripple Skymont.

An architecture that introduced novel decoder to address x86's fundamental weakness and a few years after the competitor is adopting is not far off from being dramatically better. "Revolutionary" architectures hardly work out in practice. Itanium was revolutionary. Bulldozer wasn't but a huge departure from the past. So was Netburst.

LionCove splits the scheduler into separate ones for FP and Integer, which gives the transition from 5 ports (3xFP/ALU and 2xALU) to 10 ports (4xFP + 6xALU). Absolutely, Lion Cove adds 1 ALU port (+20%), 1 FP port (+33%), 1 AGU port (+20%) and 2 decoding pipelines (+33%), gaining an average of +9% higher IPC.
Even though LionCove increases the number of FP-ALU ports from 5 to 10, it absolutely gains 1 FP, 1 ALU and 1 AGU. Of course, the behavior will be different depending on the application.

Zen5 adds 2x ALU ports(+50%) for a total of 6, 1x AGU port(+33%) for a total of 4, and 2x 4-Wide decoding(+100%) for a total of 8-Wide, gaining an average of +16% IPC.

Skymont adds 1(3-Wide) decoding cluster(+50%) for a total of 9-Wide, 2 FP ports(+100%) for a total of 4, 4 ALU ports(+100%) for a total of 8, gaining IPC INT 30%+ and FP 70%+.

LionCove, despite larger buffers and control logic, adds one ALU, one FP and one AGU. I think this is quite conservative due to the redesign of the execution engine. According to the slides, P-Core will gain a 12-Wide, 8x FP and 10x ALU decoder in the future.

AMDK11 · Oct 13, 2024

poke01 said:
Run CB2024 only on SKT to find out the Skymont performance in FP.

do we really? Redwood cove did it first?

so logically speaking then the 2026 e-core will surpass Lion cove?

No, LionCove is the first Intel core since 1995 to introduce separate schedulers and pipelines for FP and separate ones for ALU. The tiles add to this a delay compared to RaptorCove.

cannedlake240 · Oct 13, 2024

DavidC1 said:
"Revolutionary" architectures hardly work out in practice. Itanium was revolutionary. Bulldozer wasn't but a huge departure from the past. So was Netburst.

Not revolutionary performance or efficiency wise. Of course given lower latency memory and faster L3 Skymont could've been even better but it's more or less in line with AMD, Arm etc.

DavidC1 · Oct 13, 2024

poke01 said:
so logically speaking then the 2026 e-core will surpass Lion cove?

Doesn't that also support rumors that they combined the team under the leadership of the current E core Chief Architect?

Of course I don't know for sure. But Raichu says there's already some front end changes in Darkmont. 4-5% improvement like in Crestmont would close the per clock gap compared to Lion Cove.

There is a point though where it comes so close that even if isn't the highest performing core, you can replace most of your lineup with it. Even for Arrowlake Intel says now workloads prioritize running on E cores first, because of the performance.

What I would like to see is the L1i cache doubled to 128KB which would also improve power efficiency. The L1i is used for caching length of the instructions too on the Monts post-Grace.

cannedlake240 said:
Not revolutionary performance or efficiency wise. Of course given lower latency memory and faster L3 Skymont could've been even better but it's more or less in line with AMD, Arm etc.

Yup. The goal they can still reach is Apple Mx efficiency, which might be doable if they keep being lackluster in gains.

I do believe some of the lackluster gains are due to what I call "AI brain drain" or all the capable people working on AI chip projects, including Jim Keller.

AMDK11 · Oct 13, 2024

DavidC1 said:
Doesn't that also support rumors that they combined the team under the leadership of the current E core Chief Architect?

Of course I don't know for sure. But Raichu says there's already some front end changes in Darkmont. 4-5% improvement like in Crestmont would close the per clock gap compared to Lion Cove.

There is a point though where it comes so close that even if isn't the highest performing core, you can replace most of your lineup with it. Even for Arrowlake Intel says now workloads prioritize running on E cores first, because of the performance.

What I would like to see is the L1i cache doubled to 128KB which would also improve power efficiency. The L1i is used for caching length of the instructions too on the Monts post-Grace.

Yup. The goal they can still reach is Apple Mx efficiency, which might be doable if they keep being lackluster in gains.

I do believe some of the lackluster gains are due to what I call "AI brain drain" or all the capable people working on AI chip projects, including Jim Keller.

What changes took place inside Intel and the merger of the P and E teams is one thing, but interpreting it without knowing the details is just hypotheses and theories.

My hypothesis is that the P and e cores are supposed to be more aligned for ISA. The fact that the ideas of some can migrate to the other and vice versa is nothing extraordinary because both work for Intel. Internally, various solutions, techniques are constantly being developed and simulations are being carried out to implement solutions in subsequent generations.

Are we now splitting hairs over which team the man will lead the merged team? It's almost like a kindergarten argument because that robot is bigger and stronger.

People who leave or new people work on all projects. This is less important.

The most important and interesting thing will be analyzing the current and next generations and what changes they will bring. Which is fascinating.

cannedlake240 · Oct 13, 2024

DavidC1 said:
What I would like to see is the L1i cache doubled to 128KB which would also improve power efficiency. The L1i is used for caching length of the instructions too on the Monts post-Grace.

Yep, even the Apple E cores have L1i twice as large. Maybe with the next density increase they can finally afford it. However Arm has been using the 64Kb L1 setup for years now...

DavidC1 said:
The goal they can still reach is Apple Mx efficiency

It firstly has to weather through Intels decisions under financial crisis mode lol

alcoholbob · Oct 13, 2024

cannedlake240 said:
Yep, even the Apple E cores have L1i twice as large. Maybe with the next density increase they can finally afford it. However Arm has been using the 64Kb L1 setup for years now...

It firstly has to weather through Intels decisions under financial crisis mode lol

I mean why even need a density increase? Did Intel really develop Adamantine cache with no intent of using it other than offering to license it to 3rd parties? Or do they really think the demand is so low they can't even make back their costs by putting it into actual CPUs?

shiznit · Oct 13, 2024

Apple can mandate a 16KB memory page in macOS/iOS and then build a massive L1. Intel and AMD have to support 4KB pages.

poke01 · Oct 13, 2024

shiznit said:
Apple can mandate a 16KB memory page in macOS and then build a massive L1. Intel and AMD have to support 4KB pages.

maybe Microsoft can add 16kB to Windows and use emulation for 4kB pages. This way Intel and AMD can move to 16KB.

Edit: it’s just not feasible.

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Senior member

Attachments

Senior member

Diamond Member

Golden Member

Diamond Member

Senior member

Senior member

Golden Member

Lifer

General Overview​

Frontend Improvements​

Instruction Fetch and Decode​

Memory and Cache Enhancements​

Simultaneous Multi-Threading (SMT)​

Senior member

Senior member

Golden Member

Senior member

Golden Member

Senior member

Golden Member

Platinum Member

Senior member

Senior member

Senior member

Golden Member

Senior member

Senior member

Diamond Member

Senior member

Platinum Member

General Overview

Frontend Improvements

Instruction Fetch and Decode

Memory and Cache Enhancements

Simultaneous Multi-Threading (SMT)