Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

DZero · Oct 15, 2024

DavidC1 said:
No Skymont based successor yet. The next one is Twin Lake, which is a refresh of Alderlake-N.

Twin Lake? Wait, what changes will have? It will have Dual channel? If that so, won't be a refresh after all.
Also, 12 core config anyone?

DavidC1 · Oct 15, 2024

DZero said:
Twin Lake? Wait, what changes will have? It will have Dual channel? If that so, won't be a refresh after all.
Also, 12 core config anyone?

No it's almost exactly the same. Probably 100MHz clock bump.

Hulk · Oct 15, 2024

coercitiv said:
Here's a simple comparison based on the LNL floor plan. Two of those NPU NCEs would almost cover an entire Skymont cluster.

View attachment 109447

Today, from a consumer point of view, the NPU just adds to the weight of the chip. MS failed to deliver anything of substance this year, and by the time they do come up with cool features we'll probably have a new generation of chips anyway. Today's chips need to have NPUs so that devs can count on the functionality, but whether they need this much NPU is debatable in my opinion (as a simple consumer, the one who's supposed to pay for this as a product). There's a high chance this hardware will become obsolete before the really good AI features come online.

I'll stop here as this was supposed to be just an observation to @Hulk 's commentary about P and E core configs in Lunar Lake... and it's borderline a rant now.

I think your point is valid. AI in the box is being pushed on us at the expense of transistors we could actually use, or additional money in our pocket.

How useful is such a tiny NPU when the big ones are requiring multiple mobile nuclear reactors for electricity? I mean, seriously, what can they actually do that is useful? Remove objects from photos faster? Okay, yes that could be kind of nice to have, but how much faster than a decent GPU?

Hulk · Oct 15, 2024

ShimmerBlade said:
https://twitter.com/x/status/1846245804966859195
Panther Lake smiles...

Do we have any photos of Pat showing off 20A silicon? If so, then this photo don't impress me much, to borrow a phrase from Shaina Twain.

DZero · Oct 15, 2024

Sorry if I am ignorant but 18A which is equivalent?

Saylick · Oct 15, 2024

DZero said:
Sorry if I am ignorant but 18A which is equivalent?

Maybe someone more knowledgeable can chime in, but compared to TSMC it's somewhere around N4P to N3B, I believe. Depends on the metric (perf/W, density).

Edit: Was going through the Leading Edge Foundry Node Advances thread because I remember someone did the comparison, but I couldn't readily find one in the last few pages of the thread.

Kepler_L2 · Oct 15, 2024

Saylick said:
Maybe someone more knowledgeable can chime in, but compared to TSMC it's somewhere around N4P to N3B, I believe. Depends on the metric (perf/W, density).

Edit: Was going through the Leading Edge Foundry Node Advances thread because I remember someone did the comparison, but I couldn't readily find one in the last few pages of the thread.

TSMC says it's comparable to N3P.

OneEng2 · Oct 15, 2024

GAA and BSPD have advantages beyond the obvious in 18A (ie more than just more dense and more power efficient). It is my understanding that it allows much more flexible design choices.

The overall performance capability of 18A designs may well exceed the expectations based on the raw metrics we are used to using because of this.

DavidC1 said:
Manufacturing process won't result in a device with better battery life. That was true in the P3 days without advanced power management. Process basically only helps in load.

System-level engineering is required to get good battery life, and Pantherlake loses few key factors that Lunarlake has. It's probably going to be better than the horrible regressions of Alderlake-Raptorlake era but that's not saying much.

@adroc_thurston BoM is not the only important thing. If they lose marketshare again to Qualcomm in PTL-U then few $ difference in BoM won't matter, because they'll lose entire chip being in a design. A 10 year old can tell you 10% lower margin is preferable to zero revenue.

Same backward thinking as Otellini losing iPhone deal.

There are only few notable jumps. Pentium M, Haswell-Broadwell, Lunarlake. None of which are process related. Arrandale = regression, Alder/Raptor = regression.

No Skymont based successor yet. The next one is Twin Lake, which is a refresh of Alderlake-N.

All good points; however, I wouldn't say that process has no effect on battery life. That is just silly. It has an effect for certain since it allows lower power for the same performance .... if the chip designer decides to use it that way vs. getting more performance for the same battery life.

DavidC1 · Oct 15, 2024

OneEng2 said:
All good points; however, I wouldn't say that process has no effect on battery life. That is just silly. It has an effect for certain since it allows lower power for the same performance .... if the chip designer decides to use it that way vs. getting more performance for the same battery life.

The effect is minimal. You are talking 5% at best.

Load will saturate TDP so you have crap battery life anyway, and people don't care about extending that by 10-20% over better performance. Bursty workloads go nowhere near saturating TDP even at the peak, where it's there for 2-3% of the time.

GAA and BSPD have advantages beyond the obvious in 18A (ie more than just more dense and more power efficient). It is my understanding that it allows much more flexible design choices.

AMD had copper interconnect in 0.18u but Intel's transistor performance was 20-30% ahead. Checking boxes is one thing, but you still need to do work to do better.

Regarding 18A: Roughly equal density to N3, and beating performance in chips that need high performance. In low power environments it's probably close.

Saylick · Oct 15, 2024

Kepler_L2 said:
TSMC says it's comparable to N3P.

Ah, gotcha. Thanks. I recalled that it straddled between two of TSMC's node families, just forgot which two.

DavidC1 · Oct 15, 2024

Saylick said:
Ah, gotcha. Thanks. I recalled that it straddled between two of TSMC's node families, just forgot which two.

I think it's better in performance for Intel's super high clocked desktop lines, but will equal or possibly fall behind for low power mobile, supporting their own statement that they won't have a mobile-oriented process until 18A-P and 14A.

Density wise it's only 30% over Intel 3(which itself is 10% over Intel 4, IF you use the HD library), so at best it's N3.

Saylick · Oct 15, 2024

DavidC1 said:
I think it's better in performance for Intel's super high clocked desktop lines, but will equal or possibly fall behind for low power mobile, supporting their own statement that they won't have a mobile-oriented process until 18A-P and 14A.

Density wise it's only 30% over Intel 3(which itself is 10% over Intel 4, IF you use the HD library), so at best it's N3.

Right, and Intel revised Intel 18A performance estimates as being 15% faster than Intel 3. Previously it was Intel 20A was 15% faster than Intel 3, with Intel 18A being an additional 10% over Intel 20A, if I recall correctly.

adroc_thurston · Oct 15, 2024

DavidC1 said:
BoM is not the only important thing

It is very very very important.

DavidC1 said:
A 10 year old can tell you 10% lower margin is preferable to zero revenue.

They're getting a lot more revenue per design if it's not covered in expensive bling.
Hope that helps!

poke01 · Oct 15, 2024

2025 will be fun. It will make or break so many companies. Intel should be fine with PTL if 18A is good, Apple should have no issues too but AMD and Qualcomm don't have anything till Q1 2026. So at least for QC, they need to show they belong in the high-end laptop space as X Elite isn't selling so well.

511 · Oct 15, 2024

DavidC1 said:
Manufacturing process won't result in a device with better battery life. That was true in the P3 days without advanced power management. Process basically only helps in load.

System-level engineering is required to get good battery life, and Pantherlake loses few key factors that Lunarlake has. It's probably going to be better than the horrible regressions of Alderlake-Raptorlake era but that's not saying much.

@adroc_thurston BoM is not the only important thing. If they lose marketshare again to Qualcomm in PTL-U then few $ difference in BoM won't matter, because they'll lose entire chip being in a design. A 10 year old can tell you 10% lower margin is preferable to zero revenue.

Less BOM is something preferred by OEM the main thing is PMIC which they will be loosing I don't know if it will be optional but Qualcomm doesn't have on package Ram to begin with their efficiency is heavily reliant on the 6-8 PMIC !! they use alongside the SOC Design

511 · Oct 15, 2024

Kepler_L2 said:
TSMC says it's comparable to N3P.

I will say than it is slightly better than N3P than.

competitors always try to show their competitors in worse light so slightly better than N3P adjustment for TSMC Downplaying

dttprofessor · Oct 16, 2024

Density isn't the top target, efficiency & performance shouled be.

511 · Oct 16, 2024

dttprofessor said:
Density isn't the top target, efficiency & performance shouled be.

Density should be one of the top target it's PPA fora reason they have bit of room in density to grow vs N3 so they should after that yeah it's going to be lot lower

Magio · Oct 16, 2024

511 said:
I will say than it is slightly better than N3P than.

competitors always try to show their competitors in worse light so slightly better than N3P adjustment for TSMC Downplaying

Yeah, TSMC conceding it's about as good as the best node they will have at the time (since N2 isn't going into HVM until a while later) is the kind of things companies say when the competitor is actually going to be better.

If Intel sticks to those deadlines and to those performance targets it would be a huge deal, the first time in god knows how long that the best node in HVM isn't TSMCs. Sure, N2 is likely to retake the crown not too long after but just making TSMC sweat for it is something no one has done in a while.

Of course there's a few caveats, such as the capacity Intel will have on 18A which will be no match for TSMCs capacity on N3P and then N2 or unknowns as to 18A's costs and yields.

511 · Oct 16, 2024

Lame Cove + Chadmont
ST-909
MT-18964

Intel Core Ultra 9 285K @ 5486.69 MHz - CPU-Z VALIDATOR

[69c8c6] Validated Dump by Soup (2024-10-16 08:38:05) - MB: ASRock Z890 Steel Legend WiFi - RAM: 32768 MB

valid.x86.fr

Hulk · Oct 16, 2024

That core voltage seems high for 5.5 GHz, especially considering we are on a smaller node. I hope the actual core voltage as read by hardware info is much lower.

gaav87 · Oct 16, 2024

Intel Core Ultra 9 285K @ 5300 MHz - CPU-Z VALIDATOR

[ump56p] Validated Dump by Shasho (2024-10-12 23:07:33) - MB: Asus ROG MAXIMUS Z890 EXTREME - RAM: 32768 MB

valid.x86.fr

https://valid.x86.fr/dj4p8a

gaav87 · Oct 16, 2024

SolidQ · Oct 16, 2024

MLID speaking with Intel Engineer

cebri1 · Oct 16, 2024

SolidQ said:
MLID speaking with Intel Engineer

Lol.

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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