Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

AMDK11 · Oct 16, 2024

DavidC1 said:
That also depends heavily on the application. Here's one for Nehalem

Nehalem - Everything You Need to Know about Intel's New Architecture

www.anandtech.com

It also assumes the skill of the teams are same.

Just cause it's not a catastrophic failure doesn't mean it cannot be a failure either.

Haswell was 10%, and Skylake was 10%. The design, methodology and the configuration of the team needs to be flipped upside down. They were coasting back then!

What if Intel decided Willamette was a 15 stage pipeline part clocking at 1.2GHz with 2 decoders and 16KB L1D instead? What if Prescott was a 25 stage pipeline part rather than 31?

We're in an era of low process gains now, and it requires more effort, and greater cost to do it. Thus increasingly every step they take needs to be taken into account. Mini-Willamette is still a failure.

Pentium 4 never had more than a 1-Way decoder and even in its last incarnation it was not intended to have a higher IPC but to achieve even higher clock speeds.

Compared to GoldenCove, LionCove, despite dividing the execution engine into a separate one for FP and a separate one for ALU and increasing the total number of execution ports from 5 to 10, absolutely gains only one FP, ALU and AGU unit.

I would reserve the final verdict until independent tests.

DavidC1 · Oct 16, 2024

AMDK11 said:
Pentium 4 never had more than a 1-Way decoder and even in its last incarnation it was not intended to have a higher IPC but to achieve even higher clock speeds.

And this was my point, which is that if they did less of "Netburst" by going with a 2-wide on Willamette rather than 1-wide, and by only having 15 stage pipeline rather than 20, it still would have proved to be a subpar product. Less bad is still not good.

Back in the P4 days it was easy to scale down, and you got huge benefits from a new process. Yet Netburst still did not make sense. Bulldozer did not make sense. Nowadays the gains are few and much more difficult. So even doing little bad, doing little-Netburst and little-Bulldozer is bad.

OneEng2 · Oct 16, 2024

DavidC1 said:
That also depends heavily on the application. Here's one for Nehalem

Nehalem - Everything You Need to Know about Intel's New Architecture

www.anandtech.com

It also assumes the skill of the teams are same.

Just cause it's not a catastrophic failure doesn't mean it cannot be a failure either.

Haswell was 10%, and Skylake was 10%. The design, methodology and the configuration of the team needs to be flipped upside down. They were coasting back then!

What if Intel decided Willamette was a 15 stage pipeline part clocking at 1.2GHz with 2 decoders and 16KB L1D instead? What if Prescott was a 25 stage pipeline part rather than 31?

We're in an era of low process gains now, and it requires more effort, and greater cost to do it. Thus increasingly every step they take needs to be taken into account. Mini-Willamette is still a failure.

I believe, based on following this dance for the last 30 some odd years like the geek I am, that Intel has gotten into the habit of lazy design being backed up and overcome by outstanding process technology. Netburst was SO bad an idea that even with a crazy good lead in process technology over AMD it was STILL losing in performance (and couldn't even begin to do real dual core or 64 bit). By going back to an architecture more like PIII, Intel was able to pummel AMD with Core 2. This continued up until Ryzen (and even then some).

The problem with this strategy ends up being the exponential cost of moving to the next node.... that eventually bankrupts you if you are trying to stay 2 die shrinks ahead of everyone else (Like Intel once was able to do).

I suspect you get kinda lazy in design when you have literally 2 times the transistor and power budget of your competitors.

Now we are seeing an age where being able to create a competitive CPU while a process behind forces your competitor into crazy high risk, and terrible margins. I think you are going to see a re-energized Intel in the next 2 years. Lets give the boys in blue a chance eh?

FYI, I have been an AMD fan for the past 40 years (since they started making x86 clones), so I am hardly blinded by Intel propaganda or anything like that.

Hulk · Oct 16, 2024

Raptor Lake ST benchmark scores were/are basically fairy dust. Sure you can run "stock" 6-6.2GHz, but not for long. The voltage required for those favored cores will quickly cook the CPU.

As I've written many times here:

1. Intel's first problem is they are competing in ST (and MT to some extent) against the previous generations unrealistic frequency and scores.
2. Their second problem is that there is additional latency with the move from monolithic to tiles.
3. Their third problem is the removal of HT, which seemingly makes it hard to reach MT performance of the previous generation especially when coupled with #2.

It's still pre-release so how is ARL doing?

1. The reduced clocks of ARL vs RPL, coupled with tile latency, is making it difficult for Intel to surpass or possibly even match the previous generation in ST. Not to make excuses, but ST benchmark performance due to "favored cores" is CPU cooking and basically useless in the real work on real applications. More ST (IPC) out of Lion Cove would of course have been better but I don't think ST will hurt many application benchmarks because there are no applications that use 1 or 2 cores.

2. As noted above this appears to be more of an issue with moving the P cores ahead rather than the E cores.

3 Before somewhat reliable performance leaks and Intel's performance information came out I thought it impossible Intel to match, much less beat the 14900K MT performance with a 8+16 design not including HT. I was wrong. Very wrong. Skymont is a resounding success and is responsible for amazing ARL MT performance. Furthermore, the super area efficient Skymont clusters are somewhat of an ace up Intel's sleeve. If they can move the needle on the P's a bit they are looking to be very competitive moving forward.

Hulk · Oct 16, 2024

OneEng2 said:
I believe, based on following this dance for the last 30 some odd years like the geek I am, that Intel has gotten into the habit of lazy design being backed up and overcome by outstanding process technology. Netburst was SO bad an idea that even with a crazy good lead in process technology over AMD it was STILL losing in performance (and couldn't even begin to do real dual core or 64 bit). By going back to an architecture more like PIII, Intel was able to pummel AMD with Core 2. This continued up until Ryzen (and even then some).

The problem with this strategy ends up being the exponential cost of moving to the next node.... that eventually bankrupts you if you are trying to stay 2 die shrinks ahead of everyone else (Like Intel once was able to do).

I suspect you get kinda lazy in design when you have literally 2 times the transistor and power budget of your competitors.

Now we are seeing an age where being able to create a competitive CPU while a process behind forces your competitor into crazy high risk, and terrible margins. I think you are going to see a re-energized Intel in the next 2 years. Lets give the boys in blue a chance eh?

FYI, I have been an AMD fan for the past 40 years (since they started making x86 clones), so I am hardly blinded by Intel propaganda or anything like that.

For me the astounding fact about Netburst is that so many super smart people can get lost in an area they know so well, and have lived in and studied most of their lives, yet they still end up taking a devistatingly wrong turn on a super highway with no exit for 50 miles, which made them late for an exceedingly important event.

OneEng2 · Oct 16, 2024

AMDK11 said:
Pentium 4 never had more than a 1-Way decoder and even in its last incarnation it was not intended to have a higher IPC but to achieve even higher clock speeds.

Compared to GoldenCove, LionCove, despite dividing the execution engine into a separate one for FP and a separate one for ALU and increasing the total number of execution ports from 5 to 10, absolutely gains only one FP, ALU and AGU unit.

I would reserve the final verdict until independent tests.

Indeed. Netburst was some executives wet dream where consumers would purchase a CPU because Intel had spent decades training people that higher clock = higher performance (linearly). It was the most stupid idea in the history of CPU's (although Itanic rates a close second in my book).

I guess it never occurred to Intel execs that AMD would simply abandon the HZ naming convention.

While Lion Cove is an improvement over Golden Cove in the respects you point out, it is also on a better process than Golden Cove and likely has a higher transistor budget. After all this, it is only a marginal increase in IPC ..... and doesn't appear to clock as high .... thus the problem.

You are spot on with the last statement though. Final verdict will lie with the independent (and quite extensive I suspect) tests.

cannedlake240 · Oct 16, 2024

OneEng2 said:
For Intel, I have always heard that SMT only provided 10-15%. AMD's Ryzen cores seem to get 20-30% from their SMT implementation

Blender happens to be a workload that does benefit greatly from HT enabled P cores. Also it seems LionCove hasn't improved much in this workload. Add to that a slight decrease in all core frequency from 14900KS

OneEng2 said:
would a die with only Skymont still face thermal limiting in a dense DC chip?

Server cores don't run at 4.6Ghz all core

OneEng2 · Oct 16, 2024

Hulk said:
For me the astounding fact about Netburst is that so many super smart people can get lost in an area they know so well, and have lived in and studied most of their lives, yet they still end up taking a devistatingly wrong turn on a super highway with no exit for 50 miles, which make them late for an exceedingly important event.

LMFAO. Gave me a good laugh Hulk .

I don't know anyone from that design team, but it is my belief (because I know how smart these kinds of engineers really are) that the "orders from on-high" were given and likely more than one brave engineer provided ample evidence that the company was about to make a "devastatingly wrong turn on a super highway with no exit for 50 miles" .

What I DON'T believe is that Lion Cove is like that at all.

Hulk said:
Raptor Lake ST benchmark scores were/are basically fairy dust. Sure you can run "stock" 6-6.2GHz, but not for long. The voltage required for those favored cores will quickly cook the CPU.

As I've written many times here:

1. Intel's first problem is they are competing in ST (and MT to some extent) against the previous generations unrealistic frequency and scores.
2. Their second problem is that there is additional latency with the move from monolithic to tiles.
3. Their third problem is the removal of HT, which seemingly makes it hard to reach MT performance of the previous generation especially when coupled with #2.

It's still pre-release so how is ARL doing?

1. The reduced clocks of ARL vs RPL, coupled with tile latency, is making it difficult for Intel to surpass or possibly even match the previous generation in ST. Not to make excuses, but ST benchmark performance due to "favored cores" is CPU cooking and basically useless in the real work on real applications. More ST (IPC) out of Lion Cove would of course have been better but I don't think ST will hurt many application benchmarks because there are no applications that use 1 or 2 cores.

2. As noted above this appears to be more of an issue with moving the P cores ahead rather than the E cores.

3 Before somewhat reliable performance leaks and Intel's performance information came out I thought it impossible Intel to match, much less beat the 14900K MT performance with a 8+16 design not including HT. I was wrong. Very wrong. Skymont is a resounding success and is responsible for amazing ARL MT performance. Furthermore, the super area efficient Skymont clusters are somewhat of an ace up Intel's sleeve. If they can move the needle on the P's a bit they are looking to be very competitive moving forward.

I totally agree with your assessment.

Based on all that Intel had to make up for in moving to the Arrow Lake design (they were behind in many ways architecturally as you pointed out), Arrow Lake and Lunar Lake look pretty good.... and on the right track to me.

Still, they aren't all the way out of the woods yet.

It still looks like 9950x is able to best Arrow Lake's best in single and multi-thread .... and it is doing it from a process node behind (N4P vs N3B). I am not sure, but I suspect that Zen 5c is more power efficient (more IPC/Watt) than Skymont while Skymont has more IPC per mm2. Still trying to get my head around this one.

Only 1 more week until we find out for sure.

OneEng2 · Oct 16, 2024

cannedlake240 said:
Blender happens to be a workload that does benefit greatly from HT enabled P cores. Also it seems LionCove hasn't improved much in this workload. Add to that a slight decrease in all core frequency from 14900KS

Server cores don't run at 4.6Ghz all core

It will be interesting to see the comprehensive suite of MT benchmarks.

What I am wondering is what kind of performance/watt Skymont can get in a DC chip.

In the desktop and laptop markets, die size is very important because you can't ask a consumer to buy a computer chip for 5 figures and beyond.

In the DC market, such margins exist and the value of performance greatly overcomes silicon cost.

With these halmarks in place, the real issue will come down to something that has nothing to do with either of these, but rather licensing cost per core.

The cost of most servers is mostly in the licensing costs, not the hardware (despite the crazy prices these big chips command). This cost is ALSO annual in most cases (just to add insult to injury).

Because of this, the value proposition in DC comes down to:

1) Performance per core (because of the licensing costs)
2) Performance per watt (because the cores become limited by overall power requirements and heat density which effect their ability to achieve the first point)

SMT doesn't count in "core count" so it is pretty crazy not to include it in a DC chip.

DavidC1 · Oct 16, 2024

AMDK11 said:
Pentium 4 never had more than a 1-Way decoder and even in its last incarnation it was not intended to have a higher IPC but to achieve even higher clock speeds.

There was a popular website during those days called Geeks.com or something and there may have been a rumor that Prescott widened to 3-wide. Looks like my memory got stuck there.

It's interesting why they stuck to a 1-way decode when doubling that up to 2-way would have increased performance dramatically in lots of applications. It's not until 3-way where diminishing returns really kick in.

Hulk said:
For me the astounding fact about Netburst is that so many super smart people can get lost in an area they know so well, and have lived in and studied most of their lives, yet they still end up taking a devistatingly wrong turn on a super highway with no exit for 50 miles, which made them late for an exceedingly important event.

Oftentimes, specialization of a field results in a very tunnel vision view.

While many may have disagreed, many also fell into the trap that clocks would somehow scale forever into eons of GHz when it's clear to a simple DIY builder of computers that based on LN2 OC results it could barely exceed 7GHz(back then), and doing that on conventional cooling is next to impossible. It's 2024 and Raptorlake with all it's tricks is degrading at a mere 6GHz.

cannedlake240 · Oct 16, 2024

OneEng2 said:
It will be interesting to see the comprehensive suite of MT benchmarks.

What I am wondering is what kind of performance/watt Skymont can get in a DC chip.

In the desktop and laptop markets, die size is very important because you can't ask a consumer to buy a computer chip for 5 figures and beyond.

In the DC market, such margins exist and the value of performance greatly overcomes silicon cost.

With these halmarks in place, the real issue will come down to something that has nothing to do with either of these, but rather licensing cost per core.

The cost of most servers is mostly in the licensing costs, not the hardware (despite the crazy prices these big chips command). This cost is ALSO annual in most cases (just to add insult to injury).

Because of this, the value proposition in DC comes down to:

1) Performance per core (because of the licensing costs)
2) Performance per watt (because the cores become limited by overall power requirements and heat density which effect their ability to achieve the first point)

SMT doesn't count in "core count" so it is pretty crazy not to include it in a DC chip.

It's unclear what their plan in with HT on server. There's rumors that after Clearwater forest there'll be no more E core Xeons. Intel might have to bring HT back at some point whether it's on LionCove or Atom successor, whichever takes over as the primary IP

DavidC1 · Oct 16, 2024

cannedlake240 said:
It's unclear what their plan in with HT on server. There's rumors that after Clearwater forest there'll be no more E core Xeons. Intel might have to bring HT back at some point whether it's on LionCove or Atom successor, whichever takes over as the primary IP

Other more well known leakers said that's wrong and the successor to Clearwater Forest, Rogue River Forest, is still on the table.

Moving to Skymont, then having a cache base tile with 288 cores of them will do very well against 128/256 Granite Rapids.

cannedlake240 · Oct 16, 2024

DavidC1 said:
Other more well known leakers said that's wrong and the successor to Clearwater Forest, Rogue River Forest, is still on the table.

Moving to Skymont, then having a cache base tile with 288 cores of them will do very well against 128/256 Granite Rapids.

Idk... Could be because of old info. It wouldn't be too surprising for Intel, they already said P core Xeon will be a lion's share of xeons for years. Most secondary products that serve smaller segments seem to be getting cancelled by intel

poke01 · Oct 16, 2024

MarkPost said:
false

yes, my mistake. Is it only up to AVX2?

DavidC1 · Oct 17, 2024

poke01 said:
yes, my mistake. Is it only up to AVX2?

No you are right. Ryzen 9 7950X supports AVX-512, but unlike Zen 5 it does it by double pumping the 256-bit units.

AMD Zen 4 AVX-512 Performance Analysis On The Ryzen 9 7950X Review - Phoronix

www.phoronix.com

DavidC1 · Oct 17, 2024

cannedlake240 said:
Intel might have to bring HT back at some point whether it's on LionCove or Atom successor, whichever takes over as the primary IP

Or... when everything moves to being based on the current E core architecture, SMT won't come back.

Read up into Eric Quinnell's talk. He goes into detail about both uop caches and SMT.

OP caches are large, complex, make branch prediction logic replicate, and use lots of power.
1. ~100-bit read/write array (vs the 16-32-bit original instruction)
2. Redundant branch prediction hardware
3. OP cache specific fetch-line buffering

Regarding SMT:

Claim: SMT in an out-of-order, virtualized, non-shared context will be beaten by singlethreaded SMP
-2x85% IPC SMP cores at ½ the size beat ~120% IPC SMT
-Full-context SMT takes >> 10% area in reality. Find a die shot (not a paper or claim) where this is untrue.
-“Noisy neighbor effect” with cross-polluting caches
-Spectre-style security problems
-HW-multi thread scheduling unable to predict SW multi-thread intent, forecasting, prefetching
-All threads must sleep before powering down
-Out-of-order resources lost to hold variable SMT retire state
-Turn off hyperthreading and see for yourself. Did you lose anything?

SMT also increases the complexity of validation, which is way more important than few mm2, because pitfalls in development can result in product cycles becoming longer, which has a knock-on effect to future lines. Then you must consider what you gain if you take the saved complexity from validation - easier development, or moving that complexity elsewhere, such as uarch.

Intel's own x86 Optimization manual says this:

This overall approach to x86 instruction decoding provides a clear path forward to very wide designs without needing to cache post-decoded instructions.

Uop cache days are limited for Intel. SMT may not be far away.

3x the core size difference in the same node. That means a 288 core Skymont spends less on core than 128 core Granite Rapids, and that's just on the client side, where the area-hogging AMX doesn't exist on Redwood Cove.

This is more than just technicals. It is a fundamental difference in ideology.

Markfw · Oct 17, 2024

DavidC1 said:
No you are right. Ryzen 9 7950X supports AVX-512, but unlike Zen 5 it does it by double pumping the 256-bit units.

AMD Zen 4 AVX-512 Performance Analysis On The Ryzen 9 7950X Review - Phoronix

www.phoronix.com

But Zen 5 has full avx-512.

poke01 · Oct 17, 2024

Does Blender CPU take advantage of AVX-512?

MoistOintment · Oct 17, 2024

OneEng2 said:
Core Ultra 9 285K retail samples benchmarked in CPU-Z and Blender — thermal throttling and limited clock speeds spoil the fun

It is still around 10% faster than Raptor Lake Refresh

www.tomshardware.com

It is interesting that it is doing so well in multi-thread. Give credit to all those praising the Skymont cores, but still, there are concerns even in multi-core.

Still not a match for 9950X in multithread despite having 4 more cores. Also, it is thermally limited even on N3B.

Thoughts?

Is it though? 101C is 4 degrees below TJMax AFAIK. And exceeding 5.5Ghz is TVB.

And for all we know, this could be tested using a cheaper cooler. We'll see when testing comes out, but if it can hit and hold 5.7Ghz on a 240 AIO, I would consider the thermals just fine.

alcoholbob · Oct 17, 2024

OneEng2 said:
Core Ultra 9 285K retail samples benchmarked in CPU-Z and Blender — thermal throttling and limited clock speeds spoil the fun

It is still around 10% faster than Raptor Lake Refresh

www.tomshardware.com

It is interesting that it is doing so well in multi-thread. Give credit to all those praising the Skymont cores, but still, there are concerns even in multi-core.

Still not a match for 9950X in multithread despite having 4 more cores. Also, it is thermally limited even on N3B.

Thoughts?

Don't 9950X usually score around 17k range in CPU-Z?

Hitman928 · Oct 17, 2024

OneEng2 said:
SMT doesn't count in "core count" so it is pretty crazy not to include it in a DC chip.

Depends on the software, some are licensed based on “core” count and don’t distinguish between physical or logical cores for licensing purposes.

MoistOintment · Oct 17, 2024

Hulk said:
For me the astounding fact about Netburst is that so many super smart people can get lost in an area they know so well, and have lived in and studied most of their lives, yet they still end up taking a devistatingly wrong turn on a super highway with no exit for 50 miles, which made them late for an exceedingly important event.

Correct me if I'm wrong, or is Netburst being a failure more hindsight is 20/20? This is years before I started following hardware, but I heard that when Netburst design first started, many believed clock speeds would just keep increasing, so focusing on clockspeed at the expense of IPC sounded like a good idea initially at the time the development started. Only later on was it discovered to be a terrible idea. Going from 2Ghz to 4Ghz is 2x performance, without any change to IPC. Intel was predicting publicly that they'd be hitting 10Ghz in a few generations.

cannedlake240 · Oct 17, 2024

DavidC1 said:
when everything moves to being based on the current

That'll be in a while... Probably 2.5 server gens

Hitman928 · Oct 17, 2024

MoistOintment said:
Correct me if I'm wrong, or is Netburst being a failure more hindsight is 20/20? This is years before I started following hardware, but I heard that when Netburst design first started, many believed clock speeds would just keep increasing, so focusing on clockspeed at the expense of IPC sounded like a good idea initially at the time the development started. Only later on was it discovered to be a terrible idea. Going from 2Ghz to 4Ghz is 2x performance, without any change to IPC. Intel was predicting publicly that they'd be hitting 10Ghz in a few generations.

Intel was right in that the FET themselves continued to scale very well in frequency. The problems they didn’t seem to anticipate is that the effect of the parasitics on achievable frequency increases faster than the achievable frequency of the FETs. Additionally, the power density becomes a major issue as you continue to scale to smaller and smaller geometries.

gdansk · Oct 17, 2024

MoistOintment said:
Correct me if I'm wrong, or is Netburst being a failure more hindsight is 20/20? This is years before I started following hardware, but I heard that when Netburst design first started, many believed clock speeds would just keep increasing, so focusing on clockspeed at the expense of IPC sounded like a good idea initially at the time the development started. Only later on was it discovered to be a terrible idea. Going from 2Ghz to 4Ghz is 2x performance, without any change to IPC. Intel was predicting publicly that they'd be hitting 10Ghz in a few generations.

Here's an editorial from the Microprocessor Report Dec 1999 which I think shows the impression of speed demons at the time:

But personally after Willamette I think they should have realized some problems but they doubled down with Prescott.

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