You must've missed Det0x's hint on page 827 eh? Its rumored that he may have one in his possession, so he might know what he's talking aboutThere is some Xitter chatter about the 9800 X3D potentially having the cache die UNDER the CCD this time, but it’s mostly stemming from AMD marketing Zen 5 X3D as being “reimagined “.
I did miss that. Was too busy making memes and I glossed right over it. Dang!You must've missed DeTox's hint on page 827 eh? Its rumored that he may have one in his possession, so he might know what he's talking about
Your scores matches what I see on Wcctech with another user on his 5800X3D + 4090 on Win 11.Nice. Yeah it seems it's not that GPU limited. My 5800x3d with -30 CO all cores (4550 Mhz max clocks) with RTX 4090 only did 33504 (despite giving a OK cinebench score of 14256):
I guess switching the GPU also plays a role (though I did use DDU). Nevertheless will try to clean some more and install updates and try again.
Whichever way you slice it, the 9900X3D score seems reallly good
My win 10 install is from 2020.3 7900XTX, one 4090, the 4090 is the 33k one !
I'm guessing freshness of OS install, running programs in background and memory setup
edit : maybe PCIe gen counts too. I'm on x470 so x16 gen3.
Any reason you measure at 1024x768 instead of 720p like others?Reran the benchmark, now in 1:1 mode (it seems slightly faster than 1:2, although I never tried equivalent of 6400@cl28 in 1:2 mode)
View attachment 109895View attachment 109896
yup should be 720p Laptop preset like the rest. Not custom like in his screenshot.Any reason you measure at 1024x768 instead of 720p like others?
To make the benchmark as GPU-limited as possible, of course. 6900xt is like 25-50% slower as compared to 7900xtx/4090, so can't really compare it anywayAny reason you measure at 1024x768 instead of 720p like others?
If the Zen 5 CCDs were capable of going on top of other silicon, that would be kinda close to making it possible to make a refresh of Zen 5 that would replace the old IOD and substrate chiplet interconnect with a new design with Zen 5 CCD being 3D mounted on top of a modern IOD (that would then get Zen 6 CCDs in the next round of desktop CPUs). And also Strix Halo being 3D.You must've missed Det0x's hint on page 827 eh? Its rumored that he may have one in his possession, so he might know what he's talking about
I dont know about all that future stuff, but at least for the L3 vias, it appears that it is indeed capable of going on top of the X3D die.If the Zen 5 CCDs were capable of going on top of other silicon, that would be kinda close to making it possible to make a refresh of Zen 5 that would replace the old IOD and substrate chiplet interconnect with a new design with Zen 5 CCD being 3D mounted on top of a modern IOD (that would then get Zen 6 CCDs in the next round of desktop CPUs). And also Strix Halo being 3D.
I wish...
If the Zen 5 CCDs were capable of going on top of other silicon, that would be kinda close to making it possible to make a refresh of Zen 5 that would replace the old IOD and substrate chiplet interconnect with a new design with Zen 5 CCD being 3D mounted on top of a modern IOD (that would then get Zen 6 CCDs in the next round of desktop CPUs). And also Strix Halo being 3D.
I wish...
I wonder how the economics would work out if AMD were to completely forego L3 on the main CCD die (saving die area) and making all the processors V-Cache, and stacking them on top of IO die.
Then, the IO die would be broken into a section of dedicated V-Cache, private to the CCD sitting above it (maintaining the low latency). Plus there would be a link to IO die for the rest of the communication. IO die could continue to be N6 based.
The alternative - Strix Halo like link between CCD and IO Die - while cheap, it is not free.
The advantage disadvantages of proposed CCD on top of IO die:
- cost of 3D stacking
+ die saving on expensive node of CCD, not suitable for SRAM to cheaper N6 node
+ every CPU already starts with V-Cache and its performance advantage
+ unlimited bandwidth and low latency to IO die
Strix Halo / Navi 31/32 fanout link:
+ cheaper than 3D stacking
- fanout link still has its own cost
- SRAM on expensive node, where it does not scale
- adding V-Cache still has the same additional cost
I know it’s probably similar for a tuned 9700x as well but my brain still struggles to comprehend it can beat a 5950x in cb r23 multi
- cost of 3D stacking
I think you are understimating the latency hit. Or maybe I am overestimating it. Either way there would be a loss in performance.
I think you are understimating the latency hit. Or maybe I am overestimating it. Either way there would be a loss in performance.
Actualy it doesnt, this will be the case for a 8C Zen 6 though, at Computerbase they have the 5950X stock at 26196 pts, but still that s impressive that it more or less match it at half the core count.I know it’s probably similar for a tuned 9700x as well but my brain still struggles to comprehend it can beat a 5950x in cb r23 multi
The problem with hybrid bonding is not cost, but capacity. The process used for it is slow, meaning that the throughput of a line doing it is not very high, meaning you have to build a lot of capacity, which is slow.
I cannot see them doing a product stack that strictly depends on hybrid bonding for all SKUs either next gen or the one after that. Not because of cost, but because you cannot magic up capacity for it.
I am not talking about eliminating L3 and replacing it mall MALL.
L3 would remain, but be entirely on 3D stacked die. The latency hit for data that appears in on-die V-Cache is apparently only about 2 cycles (tolerable for L3). V-Cache processors are already dealing with this increased latency - just fine.
The V-Cache on the bottom could be either a separate die or on the same die as IO die, just completely segregated logically.
Can't do 2000fclk anymore whea's and worse perf on my 5800x3d thank god 9800x3d comes xD
Time to sell and buy day1. It will be out of stock in Poland 100%
b650-a strix or anyone have any recommendations ?
I think I misunderstood. I thought you meant remove the L3 from the CCD and stack L3 on top of the I/O die as it currently is designed.
B650 PG Lightning, based on my experience with ASROCK Z790. Generally problem free mobos.b650-a strix or anyone have any recommendations ?
It's almost like you're really onto something here...almost like that might be the planIf the Zen 5 CCDs were capable of going on top of other silicon, that would be kinda close to making it possible to make a refresh of Zen 5 that would replace the old IOD and substrate chiplet interconnect with a new design with Zen 5 CCD being 3D mounted on top of a modern IOD (that would then get Zen 6 CCDs in the next round of desktop CPUs). And also Strix Halo being 3D.
I wish...