Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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Det0x

Golden Member
Sep 11, 2014
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Last edited:

Kepler_L2

Senior member
Sep 6, 2020
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I have to say, it's a super interesting concept. I can't really imagine it being used in server or desktop CPUs, would they really route hundreds of watts of power (total) through DDR chips?

But I'd really like to see a mobile chip where the entire CPU is placed on top of the RAM. This looks like the next logical step up from the "memory on package" era, offering power (and potentially latency) improvements.

However, it's worth noting that not every exciting packaging patent ends up being used. Remember this one:
https://www.freepatentsonline.com/20210097013.pdf
It's not a RAM chip, it's an active interposer with DDR memory controllers.
 

Joe NYC

Platinum Member
Jun 26, 2021
2,625
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I have to say, it's a super interesting concept. I can't really imagine it being used in server or desktop CPUs, would they really route hundreds of watts of power (total) through DDR chips?

But I'd really like to see a mobile chip where the entire CPU is placed on top of the RAM. This looks like the next logical step up from the "memory on package" era, offering power (and potentially latency) improvements.

However, it's worth noting that not every exciting packaging patent ends up being used. Remember this one:
https://www.freepatentsonline.com/20210097013.pdf
I think the DDR label there is just from DDR memory controller on the AIB base tile.
 
Reactions: lightmanek

MadRat

Lifer
Oct 14, 1999
11,950
272
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Longer layout times to squeeze out performance on each process perhaps? Seems like if you were to reimagine things then layout would maximize distribution of power management and heat production first with the more focused on shared access at the IO level also a high priority. You should be able to do several improvements at same time, just not as easily as the original layout that literally evolved from each previous version. Keeping the first run simple and on time is pretty important. But competition seems to force manufacturers to focus on incremental improvements over big leaps to keep risks down, too. So maybe early Zen5 performance was held back out of caution and now we are simply seeing it mature.
 
Reactions: OneEng2
Jul 27, 2020
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I am also wondering if AMD will not make X3D part of its main product line. Surely more than just games would benefit from more L3?
Yeah any workloads that re-use data a lot will benefit. The most important benefit should be in doing multiple things at once, like browsing while there's encoding going on in the background and also Discord running etc.
 

Abwx

Lifer
Apr 2, 2011
11,592
4,408
136
Computerbase updated their gaming benchmarks with power consumption
also measured.

FI the 7800X3D wich reign supreme in the gaming charts has as much as 3x the perf/watt of the least efficient contender.

 

Makaveli

Diamond Member
Feb 8, 2002
4,825
1,325
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Computerbase updated their gaming benchmarks with power consumption
also measured.

FI the 7800X3D wich reign supreme in the gaming charts has as much as 3x the perf/watt of the least efficient contender.

The power consumption of the X3D chips in those benchmarks are impressive.
 

Josh128

Senior member
Oct 14, 2022
463
750
106
And you laughed at me when i said 9800x3d will be 15-20% over 7800x3d then next day igor posted the benches and you started hyping 9800x3d with memes xD
Also check out asrock x870 RS pro wifi. I think its best bang for buck mobo right now or did you not return that mobo yet ?
Where did I laugh at you? But yes, without the obvious hefty tuning that was done in the bench Igor posted I still think the chip will struggle to achieve +15% average in gaming vs 7800X3D. 5.2GHz just wont be enough for that outside of games that already benefit from Zen 5 architecture.

I considered Asrock, but I found an unbeatable deal on a X870E Tomahawk and have it coming, so I will be returning the Pro Wifi.
 

Hitman928

Diamond Member
Apr 15, 2012
6,330
11,156
136
Kepler just posted a patent that is one level above of what I was thinking, namely, there is a separate "pair node" which sits on top of IOD / AID. This "pair node" I am guessing would be SRAM for L3.

My thinking was that there could just be a section of the bottom die dedicated to L3.



I believe others have mentioned it, but the patent itself is about putting dies face to face and "sharing" at least 1 metal layer. The patent then goes on to show/describe a bunch of different ways they could use this, the picture Keplar showed is just one example where, it seems to me, that the bottom die is used for backside power delivery and potentially contains some circuitry as well (some analog and/or Vcache). Then, the 2 stacked dies are on top of an active interposer that would contain the memory controller and other IO. In the end, they could end up using all of it, or just parts, but obviously they want the patent to cover as much as possible.

Previously, AMD has done face to back stacking.
 
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